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Observer
Observer
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Registered: ‎12-04-2019

Host memory access using DMA for PCIe IP

Hello 

Is it possible to access the host memory from the FPGA side without actually involving the host (running drivers and test programs). I am working on an application where the FPGA card can read the DDR memory of the host machine through PCIe and store it in a block RAM. I have got the design working and I am running the dma-memory-mapped test scripts in my host and it is working. How do I do it directly from the FPGA just by writing a user application using SDK?

Any ideas on this?

Thank you.

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Explorer
Explorer
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Registered: ‎08-14-2013

Re: Host memory access using DMA for PCIe IP

The Xilinx PCIe DMA cores are not really designed to work that way; they are designed primarily to be a slave to the device driver.  There are a couple of options to do what you want: one of them is to run the Xilinx PCIe DMA cores in descriptor bypass mode, where the descriptor handling logic is disabled.  However, as far as I am aware, you still need the driver to enable DMA and configure the core by writing to the PCIe BAR before the core will accept operations on the descriptor bypass interface.  Another option is to use a 3rd party or open source PCIe DMA engine that does not have this restriction, such as https://github.com/alexforencich/verilog-pcie .  Unfortunately, I don't think it's going to be as simple as just writing a few lines of code. 

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Observer
Observer
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Registered: ‎12-04-2019

Re: Host memory access using DMA for PCIe IP

Thank you @aforencich 

Will look into it the RTL IP. Anyways, I am trying the descriptor bypass mode. Will let the forum how things turn out with it.

Regards

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Explorer
Explorer
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Registered: ‎08-14-2013

Re: Host memory access using DMA for PCIe IP

Actually, one option with Xilinx IP could be to use the Xilinx CDMA core along with the AXI PCIe bridge core.  In this way, AXI reads get converted to PCIe DMA reads. 

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Observer
Observer
254 Views
Registered: ‎12-04-2019

Re: Host memory access using DMA for PCIe IP

Hmm thats interesting. Do you connect the Slave of the AXI to the CDMA and do the transfer using data received from the rx pins of PCIe?

And do you have any ideas on how and where to write the Descriptors info in the bypass mode. I have enabled the Bypass mode for both H2C and C2H channels but have not mapped into any address, I am confused with the registers I have to write to with the destination and source addresses.

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Explorer
Explorer
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Registered: ‎08-14-2013

Re: Host memory access using DMA for PCIe IP

Yeah, I think that would be the idea.  The "slave" on the PCIe AXI bridge directly accesses host memory, so yeah, you would put that on one side of the CDMA core and then use the CDMA core to perform the transfer. 

I have no idea how to use XDMA or QDMA in descriptor bypass mode.  Using them in that mode is poorly documented and as far as I could tell still requires the driver to configure things before it will work.  I also had an application that required more control over the DMA engine than XDMA provides (https://github.com/ucsdsysnet/corundum) so I spent quite a bit of time looking in to whether the XDMA core could work, and I was not very impressed with the situation.  Instead, I wrote my own DMA engine instead so I could simulate the whole system and remove the possibility of unknown roadblocks inside of black boxes I have limited documentation for, limited visibility into, limited control over, and no ability to modify. 

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Observer
Observer
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Registered: ‎12-04-2019

Re: Host memory access using DMA for PCIe IP

Thanks a lot @aforencich . I will try out the AXI PCIe IP. 

 

 

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Moderator
Moderator
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Registered: ‎05-02-2017

Re: Host memory access using DMA for PCIe IP

 

hi @naarayananrao 

 

Thanks for contacting xilinx  forums ,

I see your looking for sample code  for bypass mode , you can  generate the example design with the AXI4-Memory Mapped with Descriptor Bypass Example in vivado.

When Descriptor bypass mode is enabled, the user logic is responsible for making descriptors and transferring them in descriptor bypass interface. Mapped design with descriptor bypass mode enabled. You can select which channels will have
descriptor bypass mode. When Channel 0 of H2C and Channel 0 C2H are selected for Descriptorbypass mode, the generated Vivado® example design has descriptor bypass ports of H2C0 andC2H0 connected to logic that will generate only one descriptor of 64bytes. The user is responsible for developing codes for other channels and expanding the descriptor itself.

 

Let me know your inputs

 

chandra 

Regards
Chandra sekhar
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