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Registered: ‎05-28-2014

How can PCI irq triggered, with INT status bit cleared?


We use uio generic driver with HW composed of Xilinx FPGA PCIe device to ATOM.

The interrupts are not delivered to userspace application, but in /proc/interrupts I see that interrupts irq (number 23) is incremented

static irqreturn_t irqhandler(int irq, struct uio_info *info)
struct uio_pci_generic_dev *gdev = to_uio_pci_generic_dev(info);
<<--- we get here
if (!pci_check_and_mask_intx(gdev->pdev))
return IRQ_NONE;
<<--- But we never get here
/* UIO core will signal the user process. */

It seems that interrupt status bit is cleared, even through we got irq 23 from our device !

The device appear as following:

How can it be that irq count is incremented, but INT status bit is not set ? Note that I also verified that there are no additional irq numbered 23.

Is it an issue of FPGA device ?


Addtional info:

02:00.0 RAM memory: Xilinx Corporation Default PCIe endpoint ID
Subsystem: Xilinx Corporation Default PCIe endpoint ID
Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Interrupt: pin A routed to IRQ 23
Region 0: Memory at 91200000 (32-bit, non-prefetchable) [size=1M]
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [48] MSI: Enable- Count=1/1 Maskable- 64bit+
Address: 0000000000000000 Data: 0000
Capabilities: [58] Express (v1) Endpoint, MSI 00
DevCap: MaxPayload 256 bytes, PhantFunc 1, Latency L0s <64ns, L1 <1us
ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 10.000W
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
MaxPayload 256 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s, Exit Latency L0s unlimited
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
Capabilities: [100 v1] Device Serial Number 00-00-00-00-00-00-00-00
Kernel driver in use: uio_pci_generic


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Xilinx Employee
Xilinx Employee
Registered: ‎12-10-2013

Re: How can PCI irq triggered, with INT status bit cleared?

Hi @ransh 

Which device and core are you using?

Have you checked via ILA on the FPGA side (via the cfg_interrupt* interface) whether the interrupt enable line is high, and whether the HW / logic asserted (and deasserted) the line?   

INTx is done by Message packets, and in the FPGA logic if you indicate a "Deassert_A" then the line will be deasserted, whether the IRQ has been processed or not.  Expectation is that FPGA logic doesn't seend that deassert until serviced - but you have to have communicated that in some way to the FPGA.    My guess is that something in the FPGA user logic is deasserting prior to your host code checking the Interrupt.

Don’t forget to reply, kudo, and accept as solution.
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