09-30-2020 05:01 PM
I am using Vivado 2020.1 IP integrator with the following components
DMA Bridge for PCIe as endpoint, DDR4, and internal registers.
I am not sure how to implement the internal register interface and which IP I should be using to create access to internal registers which will be connected to AXI-Master BAR0.
A quick take video has an example of using axi_gpio.
As a user logic, which is essentially about 150, 32 bit wide internal registers that are going to be read/write type access via the PCIe interface.
Can anyone comment on how to implement such an interface? An example design would be very helpful.
11-03-2020 09:08 PM
Rule #1: If you follow Xilinx's training material, gut their example designs. They're broken. Xilinx has yet to comment on them in any errata or known issues other than acknowledging the bugs here on these forums. They've been broken since at least 2016.3, and as of 2020.1, they're still broken.
The AXI BRAM controller isn't that bad of an option. It's at least AXI compliant. It's not quite full speed, however, since it requires about 3 cycles per burst to process the burst. As a result, if you run it from an AXI-lite master, you can at best get about 25% throughput. Further, it can't handle simultaneous reads and writes. Still, it is protocol compliant as far as I can tell.
If you just want something easy to work with, feel free to try AXI-lite. It's pretty easy to work with. I personally like starting from this example when I build AXI-lite components.
Either way, good luck!
11-04-2020 09:02 AM
PCIe XDMA data bus width is 128bits wide, while the External Memory data width is 64bits.
Do you know of any example design which will handle the down conversion. I am not clear on how to handle AXI bus which is 128bit wide to the DDR4 AXI interface which is 64bit wide