08-18-2020 10:06 AM - edited 08-18-2020 10:13 AM
I want to try to let the PL read the data from DDR but I cannot find any way to configure a AXI-Full Slave port on the XDMA (DMA/Bridge Subsystem for PCI Express) ip core.
I notice that the AXI-PCIE3 (AXI Bridge for PCI Express Gen3 Subsystem) have a AXI-Full Slave port (S_AXI) but can we let FPGA access host DDR via this S_AXI port? Also, I notice XDMA can set S_AXI_LITE port while there is S_AXI_CTL on AXI-PCIE ip core. Are they equivalent? I wonder what are the major differences between these two IP cores?
Thanks in advance for your explanation! ^_^