cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
181 Views
Registered: ‎03-18-2020

How to Obtain a AXI-Full Slave Port on XDMA IP core

Jump to solution

Hi all,

 

I want to try to let the PL read the data from DDR but I cannot find any way to configure a AXI-Full Slave port on the XDMA (DMA/Bridge Subsystem for PCI Express) ip core.

I notice that the AXI-PCIE3 (AXI Bridge for PCI Express Gen3 Subsystem) have a AXI-Full Slave port (S_AXI) but can we let FPGA access host DDR via this S_AXI port?  Also, I notice XDMA can set S_AXI_LITE port while there is S_AXI_CTL on AXI-PCIE ip core. Are they equivalent? I wonder what are the major differences between these two IP cores?

Thanks in advance for your explanation! ^_^

Screenshot from 2020-08-19 01-11-10.png

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Explorer
Explorer
87 Views
Registered: ‎08-14-2013

If you want a full AXI slave that sees the host address space, then you want the AXI-PCIe bridge, not the XDMA core. 

View solution in original post

0 Kudos
1 Reply
Highlighted
Explorer
Explorer
88 Views
Registered: ‎08-14-2013

If you want a full AXI slave that sees the host address space, then you want the AXI-PCIe bridge, not the XDMA core. 

View solution in original post

0 Kudos