How to access Registers over PCIE - XDMA using AXI Lite Master Interface or DMA Bypass
we are trying to access AXI-GPIO memory mapped registers via the XDMA PCIe Block IP 4.1 from a linux PC with the xdma drivers loaded. The XDMA Block is configured for AXIS stream, the streaming part through the c2h channel works.
We connected AXI-GPIOs with an AXI SmartConnect block to the XDMA block. (see screenshot).
The kernel driver registers a device /dev/xdma0_user or /dev/xdma0_bypass, depending on the selected option. The Xilinx answer 65444 suggests to use the tool reg_rw to access the memory mapped registers.
We tried to access the individual GPIO_DATA and GPIO2_DATA registers (axi_channel_correction_x). We expected the memory mapping to be according to our attached memory map and tried this:
sudo ./reg_rw /dev/xdma0_bypass 0x40000000 w 0xFFFFFFFF
argc = 5
access type: write
access width given.
access width: word (32-bits)
character device /dev/xdma0_bypass opened.
Memory mapped at address 0x7fcac3fa0000.
Write 32-bits value 0xffffffff to 0x40000000 (0x0x7fcb03fa0000)
But we always got a memory access error. How do the mapped registers relate to the address needed for reg_rw?