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avinashc
Explorer
Explorer
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Registered: ‎10-09-2018

How to access XDMA BRAM from user logic?

Hello,

system: Artix7 (xc7a50t-3csg125), Vivado 2020.2, Win10-64bit

 

Task: I want to access BRAM memory created by XDMA IP core(BAR) to write user logic.

 

I was checking some articles and forum for this and I found out that I have to use Smartconnect /Interconnect IP and some IP block to achieve this task but  I am not quite sure how to do this exactly. 

Do I have to split AXI bus with some mux or something else I need to do?

Can someone give me brief idea about this.

 

I have generated XDMA IP core and it is working fine on my system. 

 

Thanks!

Avinash

 

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dpaul24
Scholar
Scholar
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Registered: ‎08-07-2014

@avinashc ,

Do I have to split AXI bus with some mux or something else I need to do?

MUXes cannot be used for AXI system. It is an addressable bus. Please read the AMBA AXI spec for details.

This BRAM will be within some slave address range of the AXI master. If an AXI master drives the axi addr bus with the proper address then your BRAM contents are accessable over tha AXI bus.

 

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avinashc
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Registered: ‎10-09-2018

Hi @dpaul24 ,

 

I have only 1 question and that is,

1) Can I insert my user logic to access BRAM of XDMA in XDMA example code without disturbing PCIe side logic.

So PCIe to PC will work independently and fpga to BRAM(user logic) will work independently.

I have selected AXI lite master interface and DMA bypass interface both option while generating core for BAR.

--

That was the reason I asked earlier, Only XDMA IP core is enough (to insert user logic, so PCIe and user logic will independently use BRAM) or I have to add some more IP (like Smartconnect or Interconnect)to have access to BRAM of XDMA core.

 

Thanks!

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dpaul24
Scholar
Scholar
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Registered: ‎08-07-2014

@avinashc ,

That means you want to have another AXI4/AXI4-Lite master that will access the BRAMs?

Yes you can connect, but remember that during the DMA operation, your added master cannot access the BRAMs. For system efficiency the design must be so that DMA transactions are not hampered.

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