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Visitor
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Registered: ‎03-06-2019

How to add primitives to the stage1 PBLOCK

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Hi, 

I'm using a Virtex-7 (XC7VX330TFFG1761-2) with a PCIe core in Tandem PCIe mode and I'm getting the following errors.  How do you fix this? I don't understand the instructions at the end of the error.

[Common 17-1550] Command failed: Error: The following primitive must be added to a stage1 PBLOCK
Cell "logicSubsys/pcie_subsys/EP/pcie3_7x_0_support_i/pipe_clock_i/GND" of Type "OTHERS.others.GND"
Cell "logicSubsys/pcie_subsys/EP/pcie3_7x_0_support_i/pipe_clock_i/VCC" of Type "OTHERS.others.VCC"
Cell "logicSubsys/pcie_subsys/EP/pcie3_7x_0_support_i/pipe_clock_i/mmcm_i" of Type "CLK.gclk.MMCME2_ADV"
Cell "logicSubsys/pcie_subsys/EP/pcie3_7x_0_support_i/pipe_clock_i/pclk_sel_i_1" of Type "LUT.others.LUT5"
Cell "logicSubsys/pcie_subsys/EP/pcie3_7x_0_support_i/pipe_clock_i/pclk_sel_i_2" of Type "LUT.others.LUT4"
Cell "logicSubsys/pcie_subsys/EP/pcie3_7x_0_support_i/pipe_clock_i/pclk_sel_i_3" of Type "LUT.others.LUT4"
Cell "logicSubsys/pcie_subsys/EP/pcie3_7x_0_support_i/pipe_clock_i/pclk_sel_i_4" of Type "LUT.others.LUT4"
Cell "logicSubsys/pcie_subsys/EP/pcie3_7x_0_support_i/pipe_clock_i/pclk_sel_i_5" of Type "LUT.others.LUT4"
Cell "logicSubsys/pcie_subsys/EP/pcie3_7x_0_support_i/pipe_clock_i/pclk_sel_reg" of Type "FLOP_LATCH.flop.FDRE"
Cell "logicSubsys/pcie_subsys/EP/pcie3_7x_0_support_i/pipe_clock_i/pclk_sel_reg1_reg[0]" of Type "FLOP_LATCH.flop.FDRE"
Cell "logicSubsys/pcie_subsys/EP/pcie3_7x_0_support_i/pipe_clock_i/pclk_sel_reg1_reg[1]" of Type "FLOP_LATCH.flop.FDRE"
Cell "logicSubsys/pcie_subsys/EP/pcie3_7x_0_support_i/pipe_clock_i/pclk_sel_reg1_reg[2]" of Type "FLOP_LATCH.flop.FDRE"
Cell "logicSubsys/pcie_subsys/EP/pcie3_7x_0_support_i/pipe_clock_i/pclk_sel_reg1_reg[3]" of Type "FLOP_LATCH.flop.FDRE"
Cell "logicSubsys/pcie_subsys/EP/pcie3_7x_0_support_i/pipe_clock_i/pclk_sel_reg1_reg[4]" of Type "FLOP_LATCH.flop.FDRE"
Cell "logicSubsys/pcie_subsys/EP/pcie3_7x_0_support_i/pipe_clock_i/pclk_sel_reg1_reg[5]" of Type "FLOP_LATCH.flop.FDRE"
Cell "logicSubsys/pcie_subsys/EP/pcie3_7x_0_support_i/pipe_clock_i/pclk_sel_reg1_reg[6]" of Type "FLOP_LATCH.flop.FDRE"
Cell "logicSubsys/pcie_subsys/EP/pcie3_7x_0_support_i/pipe_clock_i/pclk_sel_reg1_reg[7]" of Type "FLOP_LATCH.flop.FDRE"
Cell "logicSubsys/pcie_subsys/EP/pcie3_7x_0_support_i/pipe_clock_i/pclk_sel_reg2_reg[0]" of Type "FLOP_LATCH.flop.FDRE"
Cell "logicSubsys/pcie_subsys/EP/pcie3_7x_0_support_i/pipe_clock_i/pclk_sel_reg2_reg[1]" of Type "FLOP_LATCH.flop.FDRE"
Cell "logicSubsys/pcie_subsys/EP/pcie3_7x_0_support_i/pipe_clock_i/pclk_sel_reg2_reg[2]" of Type "FLOP_LATCH.flop.FDRE"
Cell "logicSubsys/pcie_subsys/EP/pcie3_7x_0_support_i/pipe_clock_i/pclk_sel_reg2_reg[3]" of Type "FLOP_LATCH.flop.FDRE"
Cell "logicSubsys/pcie_subsys/EP/pcie3_7x_0_support_i/pipe_clock_i/pclk_sel_reg2_reg[4]" of Type "FLOP_LATCH.flop.FDRE"
Cell "logicSubsys/pcie_subsys/EP/pcie3_7x_0_support_i/pipe_clock_i/pclk_sel_reg2_reg[5]" of Type "FLOP_LATCH.flop.FDRE"
Cell "logicSubsys/pcie_subsys/EP/pcie3_7x_0_support_i/pipe_clock_i/pclk_sel_reg2_reg[6]" of Type "FLOP_LATCH.flop.FDRE"
Cell "logicSubsys/pcie_subsys/EP/pcie3_7x_0_support_i/pipe_clock_i/pclk_sel_reg2_reg[7]" of Type "FLOP_LATCH.flop.FDRE"
This should be done in the user constraints file through the
following commands
set custom_pblock [create_pblock <pblock name>]
set_property BOOT_BLOCK 1 $custom_pblock
resize_pblock -add <site> $custom_pblock
add_cells_to_pblock $custom_pblock [get_cells <primitive name>]

 

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Visitor
Visitor
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Registered: ‎03-06-2019

Turns out my "add_cells_to_pblock $custom_pblock [get_cells <primitive name>]" had a typo in the path to the primitive name.  So, instead of returning an error that the path was bad it returned the error that the primitives must be added to a stage1 PBLOCK.

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Moderator
Moderator
734 Views
Registered: ‎02-11-2014

Hello @jamese,

It sounds like you are just missing constraints that we require for Tandem PCIe to work with the IP.

If you open the IP Example Design for your PCIe IP, you can then analyze the xilinx_pcie3_7x_ep_x8g3.xdc constraints file (yours might be called something different, it depends on PCIe IP config) and look for all the Tandem constraints included. You can then port those to your application.

Thanks,
Cory

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Visitor
Visitor
681 Views
Registered: ‎03-06-2019

Turns out my "add_cells_to_pblock $custom_pblock [get_cells <primitive name>]" had a typo in the path to the primitive name.  So, instead of returning an error that the path was bad it returned the error that the primitives must be added to a stage1 PBLOCK.

View solution in original post

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