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Visitor
Visitor
6,868 Views
Registered: ‎01-27-2010

How to put my own datas on pci-e ?

Hi, I'm a new user of Xilinx FPGA. And recently im trying to use the PCI Express Endpoint Block PLUS on Virtex-5.

I generated the IP Core in ISE 11.4, and it simulated successfully.

The problem is , how can i put my own datas on pcie bus ?

Or how to write my own program  to  connect with the IP Core ?

ps: I use VHDL.

Thanks. ^_^

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Anonymous
Not applicable
6,857 Views

When you generate the core it comes with PIO example design. Have a look at UG341 in the link below:

 

http://www.xilinx.com/support/documentation/ip_documentation/pcie_blk_plus_ug341.pdf

 

It has the details of the example design.

 

The structure of the generated files are divided between two: user application and core wrapper.

You will need to modify the user application to send your data into the core which will be passed

to the link partner via PCIe link.

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Xilinx Employee
Xilinx Employee
6,844 Views
Registered: ‎08-13-2007

You may also want to check out XAPPP859 and XAPP1026 for more complex examples:

http://www.xilinx.com/support/documentation/application_notes/xapp859.pdf (Virtex-5 FPGA Integrated Endpoint Block for PCI Express Designs: DDR2 SDRAM DMA Initiator Demonstration Platform)
http://www.xilinx.com/support/documentation/application_notes/xapp1052.pdf (Bus Master DMA Reference Design for the Xilinx Endpoint Block Plus Core for PCI Express)

Cheers,

bt

 

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Visitor
Visitor
6,826 Views
Registered: ‎01-27-2010

Thanks  and  !

 

Here is the architecture of the Core.

The only problem is , what module/entity should my own program connect with ?

Or modify ?

 

Thanks again! 

pcie_arc.bmp
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Xilinx Employee
Xilinx Employee
6,799 Views
Registered: ‎08-06-2008

XILINX_PCI_EXP_EP consists of both core instantiation and the user application instantiation. User application is not a standard module that comes with the core. This is just an example to show how the back end user application works. Therefore you might either want to replace this application or modify this application to suit your requirement.

design_hierarchy.JPG
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Visitor
Visitor
6,733 Views
Registered: ‎01-27-2010

Thanks dmsxilinx.

Now I understand the architecture of the Core.

But my problem is still unsolved.

That in order to send my own data through PCIe, what should I do ? How ?

(Since the DSPORT_INST simulation files cannot be synthesized and downloaded into FPGA)

Thanks again.

 

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Explorer
Explorer
6,624 Views
Registered: ‎10-01-2008

Hi,

 

I think you are looking for a way to send real data from PC to the board through PCIe, right?

 

The easiest way would be to use PCITree, which is a program for assessing all PCI/PCIe peripherals on Windows. Once your card is up and running on your PC, you can use it to read/write the memory space.

 

PCI tree webpage.

http://www.pcitree.de/

 

This docuemnt also contains steps for testing a PCIe design on PC (see "PciTree Testing" and "Memory Endpoint Test").

http://www.xilinx.com/support/documentation/application_notes/xapp1040.pdf

 

Hope this will help you.

 

-Yan Shun Li

 

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