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Visitor
Visitor
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Registered: ‎02-06-2020

How to read/write from XDMA bypass channel.

I'm using the xcku060(Ultrascale Kintex) to test the xdma bypass channle from/to the FPGA card through PCIE.

 

However, when I use the device file ops (https://github.com/Xilinx/dma_ip_drivers/blob/master/XDMA/linux-kernel/xdma/cdev_bypass.c) to read/write on xdma0_bypass_c2h_0 and xdma0_bypass_h2c_0, write gives no error but read gives error.

The return value of read() is always 0 and I found that the function copy_desc_data (https://github.com/Xilinx/dma_ip_drivers/blob/master/XDMA/linux-kernel/xdma/cdev_bypass.c#L104) is never exectued.

Am I supposed to use the file ops on bypass channel like the regular DMA channles (xdma0_c2h_0 and xdma0_h2c_0)? I'm using the read/write tools from (https://github.com/Xilinx/dma_ip_drivers/tree/master/XDMA/linux-kernel/tools).

Are there any sample codes regarding bypass channel?

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Moderator
Moderator
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Registered: ‎05-02-2017

Re: How to read/write from XDMA bypass channel.

 

hi kel@pony.ai ,

 

thanks for contacting xilinx  forums ,

i see your looking for sample code , you generate the example design with the AXI4-Memory Mapped with Descriptor Bypass Example in vivado.

When Descriptor bypass mode is enabled, the user logic is responsible for making descriptors and transferring them in descriptor bypass interface. Mapped design with descriptor bypass mode enabled. You can select which channels will have
descriptor bypass mode. When Channel 0 of H2C and Channel 0 C2H are selected for Descriptorbypass mode, the generated Vivado® example design has descriptor bypass ports of H2C0 andC2H0 connected to logic that will generate only one descriptor of 64bytes. The user is responsible for developing codes for other channels and expanding the descriptor itself.

 

Let me know your inputs

 

chandra 

 

Regards
Chandra sekhar
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Observer
Observer
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Registered: ‎06-18-2018

Re: How to read/write from XDMA bypass channel.

Hi Chandra,

 

We are using dma bypass channel not descriptor bypass. Base on what we're using, our example design generated "AXI4 Memory Mapped with PCIe to AXI4-Lite Master and PCIe to DMA Bypass Example Design". Is there any software example code for dma bypass?

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Visitor
Visitor
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Registered: ‎02-06-2020

Re: How to read/write from XDMA bypass channel.

Hi Chandra,

I'm actually using the AXI4 Memory Mapped with PCIe to AXI4-Lite Master and PCIe to DMA Bypass Example Design. (page98 of PG195 (v4.1) November 22, 2019 )

This example design has 3 interfaces enabled: 1. AXI lite. 2. DMA. 3. DMA bypass.

I can see the DMA is working properly however I could not find a way to make the DMA bypass working. I think this has nothing to do with the descriptor bypass you talked about, correct?

Thanks!

Ke

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Newbie
Newbie
199 Views
Registered: ‎02-14-2020

Re: How to read/write from XDMA bypass channel.


kel@pony.ai wrote:

Hi Chandra,

I'm actually using the AXI4 Memory Mapped with PCIe to AXI4-Lite Master and PCIe to DMA Bypass Example Design. (page98 of PG195 (v4.1) November 22, 2019 )

This example design has 3 interfaces enabled: 1. AXI lite. 2. DMA. 3. DMA bypass.

I can see the DMA is working properly however I could not find a way to make the DMA bypass working. I think this has nothing to do with the descriptor bypass you talked about, correct?

Thanks!

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Ke


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i'll works

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Moderator
Moderator
103 Views
Registered: ‎05-02-2017

Re: How to read/write from XDMA bypass channel.

kel@pony.ai ,

 

hi kel ,

yes your right .. bypassing the descriptor is not connected to bypass DMA .

 

genearlly we suggest to end user ,Use AXI lite master interface  to access the control registers of the peripherals used in your in design.
Use DMA bypass  AXI MM interface to actual transfer the actualll "data" by passing the DMA engine. (DMA by pass interface is just like an AXI  MM bridge of PCIE IP)

Regards
Chandra sekhar
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