How to set DFE or CTLE in Ultrascael plus PCIE IP?

[jasminetifei]

Hi,

I use "Ultrascale+ Device Integrated Block for PCI Express v1.3 IP" GEN3 x8 in XCZU7CG-2FBVB900 installed on my custom PCB as an Add-in-Card. PG213 is the document as my golden reference.

Plugging my card in the host, by lspci command I can see it is recognized as gen3x8, no problem. I did some DMA data moving from the host to the DDR4 on my card and then read it back, no problem. Everything looks working fine.

Then I sent my card to the PCI-SIG workshop to do the compliance test. The test report said: at loopback mode, without any noise, the date from equipment --> my card --> equipment is OK. But when the noise is adding, the equipment report bit-error.The noise is followed the compliance test requirement, not just any arbitrary random noise.

The testing guy told me to make sure DFE or CTLE is turned ON or needed to be set in the proper values. Indeed in PCIE SPEC there is some info about it, please see CTLE and DFE.png attached.

So I went back to PG213. The whole document only one place mention DFE, please see DFE_Preset.png attached. And it looks DFE is always ON. P213 page 308.

In 7-series or virtex6/5 the PCIE document did mention CLTE and DFE. There are even Xilinx application note discussed about it. But in Ultrascale plus document, these 2 parameters are gone.

Also PG213 page 388 debug ports there is an input named "gt_rxdfelpmreset". I don't see it is connected by anything in the example design Vivado generated.

So, how to adjust the DFE or CTLE value in ultrascale plus PCIE IP?

Please advise, thank you.

[csattar]

Hello @jasminetifei ,

in the sub modules or when we look for the GT wizard .XCI file we get Equalization mode. which Select between decision feedback equalization (DFE) mode and low-power mode (LPM) for the receiver equalization. When the Auto option is selected,
the mode is set automatically based on the channel insertion loss, where a value greater than 14 dB causes DFE to be used, otherwise LPM is used. Refer to the UltraScale Architecture GTH Transceivers User Guide (UG576) under section Equlazation for more information.

[jasminetifei]

Thank you Chandra.

You refer me to UG576, which is for Ultrascale, not Ultrascale plus.

Do you hint that PICE IP in Ultrascale plus (PG213) and Ultrascale (UG576) actually the same?

May I understand this way, when the Auto RXEQ is set to True, the DFE is selected.

Please advise, thank you.

[jasminetifei]

Actually I found the difference between "True" and "False" is in the "pcie4_uscale_plus_gt_phy_wrapper.v": The rxeq module are generated differently. Please see the attached screenshot.

When "True" is selected, 2 extra lines of coding will be generated, see red in the picture.

When "False" is selected, no these 2 lines and GT_RXPLMEN output port is opened.

It looks like only in "True" there is a chance entering LPM mode. 

That indicate when "False" it is always DFE mode, which matches PG213 description.

May I ask what exactly "AUTO" option can I choose?

Please advise, thank you.

[csattar]

hello @jasminetifei ,

Basically  selection of LPM and DFE modes should be determined based on the channel loss in your design and When the Auto option is selected, the mode is set automatically based on the channel insertion loss, where a value greater than 14 dB causes DFE to be used, otherwise LPM is used by default in the GT wizard .

[jasminetifei · Accepted solution]

Thanks Chandra,

Please correct me if I am wrong.

Enable Auto RXEQ = True, the IP will switch between LPM and DFE automatically based on the PCIE bus physical condition.

Enable Auto RXEQ = False, DFE is set and along with different insertion loss adjustment values (Chip-to-Chip, Add-in Card, Backplane).

There is no other way to configure DFE. This is the only place we can access to it.

Please advise, thank you.

[csattar]

hello @jasminetifei ,

yes your right.