cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
7,416 Views
Registered: ‎10-25-2009

How to simulate two PCIe cores

I generate an EP core and a RP core separately in my project.  In the sim top file, I instanced them as two module. Just like:

 

xilinx_pcie_2_1_rport_7x RP (

  // SYS Inteface
  .sys_clk_p(clk_sys),
  .sys_clk_n(~clk_sys),
  .sys_rst_n(sys_rst_n),

  // PCI-Express Interface
  .pci_exp_txn(rp_pci_exp_txn),
  .pci_exp_txp(rp_pci_exp_txp),
  .pci_exp_rxn(ep_pci_exp_txn),
  .pci_exp_rxp(ep_pci_exp_txp)

);

 PCIe_TOP EP(
    .sys_clk   (clk_sys),
    .RESET_N   (sys_rst_n),
   
    .pkt_gen_ren    (tc_ren_p0),
    .pkt_gen_dati   (tc_dati_p0),
    .pkt_gen_empty  (tc_empty_p0),
    .pkt_gen_ctl_ren(tc_ctl_ren_p0),
    .pkt_gen_ctl_din(tc_ctl_din_p0),
   
     // PCI-Express Interface
    .pci_exp_txn(ep_pci_exp_txn),
    .pci_exp_txp(ep_pci_exp_txp),
    .pci_exp_rxn(rp_pci_exp_txn),
    .pci_exp_rxp(rp_pci_exp_txp),
   
    .pcie_clk (user_clk),
    .pcie_reset_n (pcie_reset_n)
    );

 

But when run simulation, the RP core's user_clk_out always be "Z", it seems that the RP core doesn't work normally.

Can I use two PCIe core in the same design? 

Thank you!

0 Kudos
1 Reply
vsrunga
Xilinx Employee
Xilinx Employee
7,402 Views
Registered: ‎07-11-2011

HI,

 

Looks lke duplicate post of 

http://forums.xilinx.com/t5/PCI-Express/the-quot-user-clk-out-quot-always-be-quot-Z-quot-state/td-p/390671

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
0 Kudos