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Observer dmitril
Observer
333 Views
Registered: ‎01-17-2018

How to to disable PCIe Relaxed Ordering

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I need to disable PCIe Relaxed Ordering.
I read https://www.xilinx.com/support/answers/36589.html, but it appears to be obsolete and incorrect.
First, it says "Enable Relaxed Ordering bit in the Device Control register comes out of reset as 0", but on my Zynq endpoint (with axi bridge for PCIe Gen2 v2.8 rev 3) it appears to be set by default.
If I read "Device Control Register" at offset 0x68, it is 0x2810, even if root never modified it.

Also 36589.html says that relazed ordering bit does not change the functionality of the core, but this also appears to be incorrect - your newer modules, like axi bridge for PCIe Gen3 v3.0, do mention that transaction ordering will be different depending on whether relaxed bit is set or not.

I must guarantee a strong ordering in my PCIe application.
Please, tell me:
1. How to disable "Relaxed Ordering bit" in "Device Control register" by default?
2. How to ensure that relaxed ordering bit is never set on transactions sent by Zynq?
3. Is there anything else I should do to guarantee that relaxed ordering is disabled?

I would like to get an answer for axi bridge for PCIe Gen2 v2.8 as well as for Gen3 v3.0.

Thank you

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Xilinx Employee
Xilinx Employee
166 Views
Registered: ‎07-26-2012

Re: How to to disable PCIe Relaxed Ordering

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I checked the PG055 but there was no option to make RO be enabled. While, when Enable RO bit of Device Control register was '1' and sent a packet, RO bit (attr) of the packet was '0'. Therefore, AXI MM to PCIe Gen2 core does not support RO and it is fixed to '0' even if Enable RO bit of Device Control register is '1'.

4 Replies
Xilinx Employee
Xilinx Employee
280 Views
Registered: ‎07-26-2012

Re: How to to disable PCIe Relaxed Ordering

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As you described, Enable Relaxed Ordering in the Device Control register should be disabled. Then, the packet genertor should not set RO bit in the packet.

 

When I simply check Z-7000 PCIe, it can be disabled from the host.

 

How did you disable the bit from the host?

DevCtl_reg.png
Observer dmitril
Observer
267 Views
Registered: ‎01-17-2018

Re: How to to disable PCIe Relaxed Ordering

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Thank you for your reply.
So, are you saying that there is no way to disable Enable Relaxed Ordering bit in the Device Control register by default?
In other words it will always come out of reset as 1?
And the only way to disable it is to make a write to endpoint's Device Control register from the root/host?
And is this true for both pcie/axi bridge Gen2 and Gen3?
Thank you

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Observer dmitril
Observer
212 Views
Registered: ‎01-17-2018

Re: How to to disable PCIe Relaxed Ordering

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How to get an answer to this question?

Is there some other support channel?

Thank you

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Xilinx Employee
Xilinx Employee
167 Views
Registered: ‎07-26-2012

Re: How to to disable PCIe Relaxed Ordering

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I checked the PG055 but there was no option to make RO be enabled. While, when Enable RO bit of Device Control register was '1' and sent a packet, RO bit (attr) of the packet was '0'. Therefore, AXI MM to PCIe Gen2 core does not support RO and it is fixed to '0' even if Enable RO bit of Device Control register is '1'.