UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
5,876 Views
Registered: ‎03-03-2014

IP DMA SubSystem Simulation Crash

Jump to solution

Hi,

 

I'm working on a ZYNQ 7045 design using the PCIe DMA Subsystem.

I generated the ref design for the xdma IP associated to its configuration in my design.

I made a few modifications to put my design instead of the EP user test design.

Simulation Under Modelsim PE 10.5a with a mixte evaluation license worked perfectly, either with or without the PIPE interface. But, unlucky this evaluation license expired yesterday !

So I switched to the VIVADO simulator.

 

- Elaboration and compilation time is much longer.

- Simulation is more than two times slower than Modelsim.

 

But my problem is that simulation crashes, every time at the same place. It happends when xdma releases its axi_areset.

I can see that window's simulation processes are still alive, but Nothing changes in the GUI. Simulation pause is not responding, only VIVADO exit works. It is the same either with or without the PIPE interface.

 

So I'm stopped in my work !

 

Are there known issues with PCIe DMA subsystem simulation ?

 

Thanks.

 

Stéphane.

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Adventurer
Adventurer
9,007 Views
Registered: ‎03-03-2014

Re: IP DMA SubSystem Simulation Crash

Jump to solution

Hi,

 

First of all, happy new year to everybody !

 

Thank you XILINX for my christmas gift : Vivado 2016.4 !

 

This version solves my simulation issues.

 

Thanks again.

 

Stéphane.

View solution in original post

0 Kudos
14 Replies
Xilinx Employee
Xilinx Employee
5,844 Views
Registered: ‎11-25-2015

Re: IP DMA SubSystem Simulation Crash

Jump to solution

Hi @adeneo_sju,

 

Please provide the FPGA part number,vivado version and GUI configurations

 

I will confirm you whether it's working or not

 

Thanks,

Sethu

0 Kudos
Adventurer
Adventurer
5,835 Views
Registered: ‎03-03-2014

Re: IP DMA SubSystem Simulation Crash

Jump to solution

Hi Sethus,

 

Ok, some information:

 

- Windows 10 Professional, 64 bits

- VIVADO 2016.3

- Zynq 7045 for ZC706, xc7z045ffg900-2

 

My design is a Block design using Xilinx IP and my IPs. My Ips are designed in VHDL, but I configured the project for Verilog as there were problems with mixed language. May be it is still the problem underneath.

 

Yesterday, I used cancel simulation button, nothing happended for minutes so I left office.

And this morning I found these :

 

INFO: [Common 17-41] Interrupt caught. Command should exit soon.
FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
Time: 70000001 ps  Iteration: 2  Process: /board/EP/pcie_core_i/pcie_core_i/PCIE_CORE/xdma_0/inst/dma_top/dma_pcie_req/dma_pcie_rq/Always1387_4582
  File: /wrk/2016.3/nightly/2016_10_10_1682563/packages/customer/vivado/data/ip/xilinx/xdma_v3_0/hdl/xdma_v3_0_vl_rfs.sv

HDL Line: D:/Projets_Actifs/customer/project/2020s_fpga_mb_bram/simulation/pcie3_uscale_rp_core_top.v:10551
run: Time (s): cpu = 00:00:26 ; elapsed = 00:24:59 . Memory (MB): peak = 1323.965 ; gain = 98.648
INFO: [Common 17-344] 'run' was cancelled

 

IP configuration is :

- Basic : Advanced, X1, GT/s, 100Mhz, 125Mhz, AXI MM, Enable PIPE

- PCIe BAR : PCIe ti AXI Lite Master interface, 4 KB

- PCIe MISC : no MSI, MSI-X Capabilities

- PCIe DMA : 1, 2, 1, 32,16, 0001, 0011, 4, DMA status Ports On

 

Thank you for your help.

 

Stéphane.

0 Kudos
Xilinx Employee
Xilinx Employee
5,826 Views
Registered: ‎11-25-2015

Re: IP DMA SubSystem Simulation Crash

Jump to solution

Hi @adeneo_sju,

 

Thanks for sharing the test details.

 

With same configuration i tried running an behavioural simulation and it got stuck exactly when axi_areset_n is asserted (70032.001 ns).Please find attachment

 

In example design case,though the simulation is stuck there is no crashing issue at my end.

 

Can you confirm the failing time stamp from your end?  i can check for the rootcause in user app code and get back to you 

 

Thanks,

Sethu

 

 

Simulation Stuck.JPG
0 Kudos
Adventurer
Adventurer
5,820 Views
Registered: ‎03-03-2014

Re: IP DMA SubSystem Simulation Crash

Jump to solution

Hi Sethus,

 

Thanks for the answer.

 

As you can see, on my simulation, it freezes at 70000ns, a few clock cycles after the axi_aresetn from XDMA IP is released.

 

VIVADO does not crash, I can still use it in the other stuffs than simulation, tcl console is alive too.

 

It looks rather that simulation goes into an infinite loop.

 

xsim_stuck.png

 

Thank you.

 

Stéphane.

0 Kudos
Xilinx Employee
Xilinx Employee
5,817 Views
Registered: ‎11-25-2015

Re: IP DMA SubSystem Simulation Crash

Jump to solution

Hi @adeneo_sju,

 

Thanks its the same behaviour we both see..

 

It seems to be an issue with Xilinx PCIe DMA example design simulation.There is nothing much you can do from your end 

 

I will get back to you with the rootcause details

 

Thanks,

Sethu

0 Kudos
Adventurer
Adventurer
5,815 Views
Registered: ‎03-03-2014

Re: IP DMA SubSystem Simulation Crash

Jump to solution

Sethus,

 

Ok, I'll look for your feedback.

 

For now, I will write some documentation about my IPs :-)

 

Thank you for your help.

 

Stéphane.

0 Kudos
Xilinx Employee
Xilinx Employee
5,792 Views
Registered: ‎11-25-2015

Re: IP DMA SubSystem Simulation Crash

Jump to solution

Hi @adeneo_sju,

 

The descriptor bypass mode example design supports only 1 channel for both H2C and C2H.

If you closely look in the example design only channel 0 bypass input signals are fetched with descriptor values.

 

But in your configuration I can see 2 C2H Channels.So please change to 1 channels which is only supported

 

But after changing the configuration to 1 channels the simulation gets stuck at 112 us. Can you try once from your end

 

Moreover in 2016.3, XSIM simulator has some issue with XDMA IP. So when you face issue, it’s always good to try with Questa.Can you try if possible?

 

Thanks,

Sethu

0 Kudos
Adventurer
Adventurer
5,785 Views
Registered: ‎03-03-2014

Re: IP DMA SubSystem Simulation Crash

Jump to solution

Hi Sethus,

 

"The descriptor bypass mode example design supports only 1 channel for both H2C and C2H.

If you closely look in the example design only channel 0 bypass input signals are fetched with descriptor values."

 

I'm a little surprised with this.

As you can see in my design's hierarchy the ref design in EP section is entirely deleted and replaced with my own design.

 

hierarchy.png

 

If I dig into the xdma_0 simulation sources, I can see all of the 3 interfaces deeply Inside, so for me the simulation model handles the 3 interfaces. So if limitation for the number of bypass interfaces is in the EP ref design, not the xdma model, as I don't use it, the limitation is not supposed to be present.

 

 

 

"But in your configuration I can see 2 C2H Channels.So please change to 1 channels which is only supported

 

But after changing the configuration to 1 channels the simulation gets stuck at 112 us. Can you try once from your end"

 

To give it a try, I changed my design to have only one C2H interface, cleaned everything in BD output and simulation.

Same result exactly, it stalls at 70000 ns.

 

The simulator gives when it exits :

Time: 70000001 ps  Iteration: 2  Process: /board/EP/pcie_core_i/pcie_core_i/PCIE_CORE/xdma_0/inst/dma_top/dma_pcie_req/dma_pcie_rq/Always1387_4582

The thing is, part of this hierarchy disapears in the scopes window of xsim !

 

hier_simu.png

 

The /dma_top/dma_pcie_req/dma_pcie_rq/Always1387_4582 part should be between the inst and pcie_core_xdma_0_0_pcie_to_pcie3_wrapper_i as it is in the sources section as shown above.

The dma_top instance is the xdma_v3_0_0_dma_top module instanciated.

Don't know if it is linked or only a display bug.

 

 

 

 

"Moreover in 2016.3, XSIM simulator has some issue with XDMA IP. So when you face issue, it’s always good to try with Questa.Can you try if possible?"

 

As I said before, it worked perfectly with modelsim PE with 3 bypass interfaces.

The problem here is that as the ref design is generated only in Verilog and I design in VHDL, I need a mixte language simulator, which I don't have here in my company. So I used an evaluation license for modelsim PE mixte simulation, but it has expired !

Maybe I can try to have an evaluation licence for using questa instead of modelsim, but it will only last for a limited time.

 

Anyway, if you have any other clue, please  let me know !

 

Stéphane.

0 Kudos
Xilinx Employee
Xilinx Employee
5,782 Views
Registered: ‎11-25-2015

Re: IP DMA SubSystem Simulation Crash

Jump to solution

Hi @adeneo_sju,

 

As per PG195 description,

 

When Descriptor bypass mode is enabled, the user is responsible for making descriptors and transferring them in descriptor bypass interface.  You can select which channels will have descriptor bypass mode. When Channel 0 of H2C and Channel 0 C2H are selected for Descriptor bypass mode, the generated Vivado example design has descriptor bypass ports of H2C0 and C2H0 connected to logic that will generate only one descriptor of 64bytes. The user is responsible for developing codes for other channels and expanding the descriptor itself.

 

Thanks,

Sethu

0 Kudos
Adventurer
Adventurer
4,702 Views
Registered: ‎03-03-2014

Re: IP DMA SubSystem Simulation Crash

Jump to solution

Hi Sethus,

 

Yes, I really understand this.

 

But as I told you, I did develop code for other channels and I did expand it in the way that I replaced it all by my logic around xdma and espatially for bypass descriptor interfaces.

 

The fact is that my logic works under modelsim and not under XSIM.

 

You confirmed it earlier by saying "Moreover in 2016.3, XSIM simulator has some issue with XDMA IP".

 

So, has Xilinx identified the issue and do you intend to fix it ?

 

Thanks,

 

Stéphane.

 

 

 

 

 

0 Kudos
Xilinx Employee
Xilinx Employee
4,695 Views
Registered: ‎11-25-2015

Re: IP DMA SubSystem Simulation Crash

Jump to solution

Hi @adeneo_sju,

 

Yes i can see it working in Questa sim...

 

Yes the factory is aware of this and the PCIe DMA issues will be incrementally fixed on later release versions

 

Thanks and Regards
Sethu
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution

 

0 Kudos
Adventurer
Adventurer
4,693 Views
Registered: ‎03-03-2014

Re: IP DMA SubSystem Simulation Crash

Jump to solution

Sethus,

 

OK, is it possible to have a patch or something to fix it without having to wait for the next Vivado release ?

Maybe by going through a webcase or FAE support ?

 

Thanks.

 

Stéphane.

0 Kudos
Adventurer
Adventurer
4,685 Views
Registered: ‎03-03-2014

Re: IP DMA SubSystem Simulation Crash

Jump to solution

Hi Sethus,

 

A patch already exists.

 

https://www.xilinx.com/support/answers/68259.html

 

When applied I can go forward after the previous 70000ns.

 

Unfortunalty I get this now :

 

Ref Clk Freq: 0   User Clk Freq: 3   PCIE Link Speed: 3
[                   0] : System Reset Is Asserted...
[             4995000] : System Reset Is De-asserted...
[            70448000] : Transaction Reset Is De-asserted...
[            70452000] : Writing Cfg Addr [0x00000001]
[            78128000] : Transaction Link Is Up...
[            78136000] : TSK_PARSE_FRAME on Transmit

 frame_store_tx = 0x4a
TIMEOUT ERROR in usrapp_tx:TSK_WAIT_FOR_READ_DATA. Completion data never received.

 

It seems to be the first write in the init sequence

 

  board.RP.tx_usrapp.TSK_SIMULATION_TIMEOUT(10050);
  board.RP.tx_usrapp.TSK_SYSTEM_INITIALIZATION;

 

More precisely the

board.RP.cfg_usrapp.TSK_WRITE_CFG_DW(32'h01, 32'h00000007, 4'h1);

access in the board.RP.tx_usrapp.TSK_SYSTEM_INITIALIZATION;.

 

Stéphane.

0 Kudos
Highlighted
Adventurer
Adventurer
9,008 Views
Registered: ‎03-03-2014

Re: IP DMA SubSystem Simulation Crash

Jump to solution

Hi,

 

First of all, happy new year to everybody !

 

Thank you XILINX for my christmas gift : Vivado 2016.4 !

 

This version solves my simulation issues.

 

Thanks again.

 

Stéphane.

View solution in original post

0 Kudos