01-09-2018 02:19 PM - edited 06-18-2018 02:27 PM
Hello PCI Express Community,
If you are planning on using or are currently using Xilinx PCI Express solutions, and are experiencing any issues out of the ordinary, please first look into the following patches before posting.
AR70702 - Zynq UltraScale+ MPSoC - PS/PL PCIe Drivers - Release Notes
AR71147 - DMA / Bridge Subsystem for PCI Express (Vivado 2018.1) - Tactical patch for issue fixes
AR70012 - DMA / Bridge Subsystem for PCI Express and UltraScale+ PCI Express Integrated Block (Vivado 2017.3) - Tactical patch for issue fixes and enhancements.
AR69405 - DMA / Bridge Subsystem for PCI Express and UltraScale+ PCI Express Integrated Block (Vivado 2017.2) - Tactical patch for issue fixes and enhancements.
02-25-2019 04:42 PM - edited 02-25-2019 04:42 PM
I'm using a ZCU106 and I can tell you that things will enumerate. It is a little tricky to get the constraints going the first time. but once you get them, it should be OK.
I'm using the PL XDMA core.
02-25-2019 07:46 PM
We're using the VCU118 board with the XCVU9p, and it's actually vague what the differences are between the four banks in the x16 mode. While the one bank has no clock option that narrows it down to 3 banks, you have to use the transceiver user guide constraints between transceiver refclk routing to determine that AL* is the only solution that would actually drive x16 by the board, even though there is another solution on 3:0 that legally goes through vivado.
We haven't seen it enumerate yet. If you have a favorite troubleshooting list, please send it on.
02-25-2019 07:49 PM
So first, get a desktop that doesn't have a XEON processor. Xeon processors take too long to boot, and you will be rebooting alot.
Then, you can try to instantiate the XDMA IP, right click on it, and say "show example" or something like that.
It should create a project for you with the necessary constraints. I hope that helps.