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Visitor icogginsoda
Registered: ‎02-02-2017

Incorrect AXI4 ARSIZE/AXSIZE on PCIE XDMA core DMA transactions

I am having a problem with the PCIE XDMA core putting out an invalid AxSize signal for DMA transfers to/from the H2C/C2H AXI4 interface.


The core is configured as 256bit, but is generating an AxSize of 6 ( 64 byte/512 bit /beat) and an address increment of 512

bytes/burst.   it should output an AxSize of 5 ( 32 byte/256 bit) and address increment of 256/burst.


I am using 2016.4 and have tried with and without patch AR68512, with the same result. This design is a PCIE gen3 x8 design in an Kintex Ultrascale XCKU060 FG1156-2E ( which does not support a 512 bit AXI bus , so I can't just use 512 bits and ignore the issue).


Any one seen this/ have a fix?



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