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Explorer
Explorer
836 Views
Registered: ‎04-11-2016

Info about editing Free IP core

Hi,

when xilinx IP core (in my case PCIE gen2 lane 1 for kintex 7 series xc7k325t) hierarchy is expanded all the RTLs/XDC code are seen in read only mode in vivado. I would like to know if these RTLs/XDC code are copied into new RTL/XDC files and edit it as per need and then use it with design. Does it work same as IP core?  OR there will be restriction or license problem?

 

I am in trouble in my case when I generate PCIE IP core it automatically take QPLL of Transceiver bank but I want to use CPLL for this because QPLL and common of the same transceiver bank are already occupied by 10G. Is there any suggestion?

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3 Replies
Xilinx Employee
Xilinx Employee
781 Views
Registered: ‎12-10-2013

Re: Info about editing Free IP core

Specifically for the problem you are trying to solve, in 7-series, I would recommend you look at the "Shared Logic" option in the PCIe IP core.   There is a way to share the GT common between two cores, without having to manually edit the locked core itself.  The option pulls the GT common externally, then it can be hooked up to both cores needing it.   This is described in detail in here:

 

https://www.xilinx.com/support/answers/62267.html

 

 

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Explorer
Explorer
750 Views
Registered: ‎04-11-2016

Re: Info about editing Free IP core

hi @bethe @roym @venkata

The link you provided is the exact requirement for me but unfortunately only with simulation result and I am looking for edited code. Is there also edited code available somewhere to download?

 

Here are some info before I ask my question:

1.In the link you provided it is mentioned that:

Generally one core file set is left alone while the other is edited then added to the original unedited core design. One COMMON block is needed per quad. Remove the additional COMMON block.

 

2. https://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf

in page 319: The Channel PLL (CPLL) is recommended for Gen1 and Gen2 speeds. The Quad PLL (QPLL) is required for Gen3 speeds.

 

3. https://forums.xilinx.com/t5/Serial-Transceivers/Multiple-GTX-with-different-protocols-in-same-Quad/td-p/809314

Each GT channel has the circuitry to select the reference clock and PLL that it will use.

 

I am intending to left 10G and edit PCIE. I am using gen2 pcie so as per point 2 and point 3 I mentioned here can I even completely remove pcie common and left pcie core inputs from common (QPLLOUTCLK, QPLLOUTREFCLK and QPLLOCK ) unconnected? Does it work? or need some more works?

 

P.S. Both protocols have different reference frequency 156.25 MHz and 100 MHz.

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Moderator
Moderator
693 Views
Registered: ‎02-16-2010

Re: Info about editing Free IP core

Which vivado version are you using? In 2017.1, I find 7 series integrated block for PCI express IP has a shared logic option to have GT_COMMON in example design. This means the GT_COMMOM will be outside the PCIe IP. Have you found this option?

With this option, you can have a design where the GT_COMMON is inside 10G IP and not in PCIe IP. With the pcie core inputs from common, you can either leave them unconnected (or) connect the outputs from 10G. Since PCIe IP does not use QPLL, these inputs do not impact the GT functionality used with PCIe IP.

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