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GC
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Visitor
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Registered: ‎11-03-2020

Integrated PCIe block on Zynq ultrascale+ MPSoc configuration

Hi

I'm trying to set the configuration of the integrated PCIe in the ultrascale+ MPSoC.

I'm trying to understand how to configure the PCIe max read request parameter in the configuration space of the PCIe EP.

In addition, how to define the number of required outstanding read requests.

Thanks!

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garethc
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Registered: ‎06-29-2011

Hi @GC 

Can you review the AR:36596 which provides details on this.

https://www.xilinx.com/support/answers/36596.html

 

Thanks,

Gareth


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GC
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Registered: ‎11-03-2020

thanks Garethc

In the AR:36596 there is an explanation about what is the max read request.

My question was how to set the max read request size in the capability register, and how to determine the number of outstanding read requests for the EP device.

Thanks again

GC 

 

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garethc
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Registered: ‎06-29-2011

Hi @GC 

For the max read request you can use the SETPCI in Linux or doing configuration writes in your driver. Please see the following link that details some SETPCI commands - https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Debugging-PCIe-Issues-using-lspci-and-setpci/ba-p/1148199

For the outstanding read requests these are not handled by use and you need to handle this in your user application. There is some guidance for this in PG213 on Page 132 in Chapter 4: Designing with the Core.

Thanks,

Gareth


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