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goldshakil
Observer
Observer
438 Views
Registered: ‎11-03-2019

Interfacing Zynq7000 with a host pc

I am a totally beginner in vivado and HDL and I am trying to do a very simple task: 

1) Implement a sorting function on FPGA

2) Call that function through a host PC and send data data over PCIe. 

3) Recieve sorted data back from the FPGA

I figured out that Vivado itself is a hardware definition tool where we add IP cores and other peripherals( I have the Block Design of the board am using in Vivado). However, I am not sure about two things:

1) whether I should implement my sorting algorithm (let's say bubble sort) in SDK( after I import the hdf file) or HLS(then integrate that exported IP to my original Block Design in Vivado).

2) How can I interface the host pc with my board ( I can connect them through PCIe )

Any help, guidance , references would be helpful since I am totally new to FPGAs.
Thank you

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3 Replies
baltintop
Voyager
Voyager
417 Views
Registered: ‎06-28-2018

Hi @goldshakil 


1) whether I should implement my sorting algorithm (let's say bubble sort) in SDK( after I import the hdf file) or HLS(then integrate that exported IP to my original Block Design in Vivado).


If you want to run your algorithm on the ARM processor on your Zynq 7000 then implement it in C (in SDK), if you want to run your algorithm on the FPGA then implement it in HDL or write it in C/C++ and convert it to HDL using Vivado HLS.

goldshakil
Observer
Observer
360 Views
Registered: ‎11-03-2019

@baltintop
Then how can I call that function from the host pc (let's assume that the function is implemented in SDK).
Ps. I can connect my FPGA to a host PC using an optical PCIe cable.

My actual goal is to send some data (integers/floats) from the host PC to the FPGA , sort it on the FPGA and finally send it back in sorted order to the host PC.

But I don't know how to trigger this mechanism in the FPGA from the host PC. Any help will be really appreciated.


Thank you for the help so far

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baltintop
Voyager
Voyager
329 Views
Registered: ‎06-28-2018

Hi @goldshakil 

If the algorithm is implemented in C (SDK), which means it will run on the ARM processor, sending data to FPGA does not make sense.

If it is implemented in HDL then I suggest you first start with data transfer between the programmable logic (FPGA) and the processing system (ARM) on Zynq. Use ARM as your host computer. You can exchange data between PS and PL through the DDR memory on the board.  Connect one of the AXI ports of Zynq PS to your IP core's AXI interface. Write some data to the memory using Xil_Out32 function in SDK, process it inside your FPGA and read the results from the memory by calling Xil_In32 function. Use interrupts if necessary. Use Xilinx DMA IP core if you want to transfer data at higher rates.

I don't know much about PCIe communication, so I'll let others comment on that.