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scollinson
Contributor
Contributor
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Registered: ‎11-08-2010

Interrupt handling for XAPP1052 simulation

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I have setup a simulation of a memory transfer to my endpoint and once it is complete the endpoint (de)asserts the cfg_interrupt_n and cfg_interrupt_assert_n wires to signal completion to the rootport. My question is how do I handle this interrupt in simulation? Is there a location to write to to acknowledge the interrupt? Both the mrd_start and mrd_done signals remain high after the transaction is completed.

 

My next questions is to do with MSIs. From what I've read here on the forums these are not supported by Windows XP, is this true? I wish to atleast simulate them but cannot seem to figure out what the configuration address of the message capability regsiter is. What is the memory offset to write to in the type0 configuration space to enable MSIs?

 

Thanks,

Sam

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luisb
Xilinx Employee
Xilinx Employee
4,139 Views
Registered: ‎04-06-2010

Interrupts are generally handled by a processor, so if you're not simulating a processor, then I'm guessing your interrupt isn't going to do much in your simulation.  You have to have something polling that register to trigger an event.  Generally a processor system will do this for you automatically.

 

The MSI Enable bit is bit 0 of the Message Control for MSI register.  You can find this in the PCI Spec; which also applies for PCI Express.  If you want to find out what register it is, take a look at the core your using "PCI Configuration Space Header."  If you're using the V5 block plus core, take a look at page 22 of: 

http://www.xilinx.com/support/documentation/ip_documentation/pcie_blk_plus_ug341.pdf

 

Look for MSI Control and you should find it at Address 0x04A

 

By the way, you're also going to have to set the bus master enable bit of the Command Register.

 

Hope this helps.

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luisb
Xilinx Employee
Xilinx Employee
4,140 Views
Registered: ‎04-06-2010

Interrupts are generally handled by a processor, so if you're not simulating a processor, then I'm guessing your interrupt isn't going to do much in your simulation.  You have to have something polling that register to trigger an event.  Generally a processor system will do this for you automatically.

 

The MSI Enable bit is bit 0 of the Message Control for MSI register.  You can find this in the PCI Spec; which also applies for PCI Express.  If you want to find out what register it is, take a look at the core your using "PCI Configuration Space Header."  If you're using the V5 block plus core, take a look at page 22 of: 

http://www.xilinx.com/support/documentation/ip_documentation/pcie_blk_plus_ug341.pdf

 

Look for MSI Control and you should find it at Address 0x04A

 

By the way, you're also going to have to set the bus master enable bit of the Command Register.

 

Hope this helps.

View solution in original post