08-20-2019 09:13 AM - edited 08-20-2019 04:20 PM
We used the AC7A200T Eval board as the reference design for our design using the smaller XC7A12T for a single lane PCIe i/f. On the eval board there are no AC coupling caps on the PCIE_RX0_P (and N) input pins (page 28 of schematic).
Also, the Xilinx FAE review didn't flag that we were lacking these capacitors.But in other documents I see AC capacitors are recommened on these pins. We are failing Link Training and LTSSM is stuck at #8. Could the lack of AC capacitors be the cause of this? All electrical layout guidlines were followed for impedance matching etc. The problem also occurs with a warm PC restart.
08-21-2019 11:12 PM
No, AC coupling capacitors are NOT required on MGTRXN and MGTRXP pcie transceiver input pins in this context.
The PCIe specification says that you should AC couple the differential data signals. It also says to put the capacitors at the Tx (i.e. driver) end of the link, and not on the Rx end of the link.
The motherboard you plug your board into will have these capacitors at its drivers' outputs.
N.B. Your board does need the capacitors on the MGTTXN and MGTTXP transceiver output pins.
08-22-2019 07:44 AM
That is interesting because I had .1uf caps installed on the two MGTRXN (receive) lines and now the link is working consistently.This is a PCIe mini card that I'm testing on a standard PCIe bus on a PC using an adapter cable. Perhaps there's something there that's coming into play.