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wojtek
Adventurer
Adventurer
984 Views
Registered: ‎12-16-2008

Is Resizable BAR customisation of 7-series Integrated Block done correctly?

I suspect that there are both a bug and a misinterpretation in 7-series Integrated Block for PCIe (rev.3.3) when Resizable BAR customization is considered.

 

1) I suspect a bug in defining "Resizable BAR Capability Register". It is done by selecting wanted value in "Size Supported" field. When I select 256MB the implemented core advertises value of 0x100 in that register what corresponds to 16MB, according to PCIe standard. To get wanted 0x1000 which corresponds to 256MB (according to standard) I have to select 4GB in "Size Supported". Looks like selected value is not shifted by 4 when applying to "Resizable BAR Capability Register" - first four bits are reserved in this register.

 

2) By misinterpretation I meant how this "Resizable BAR Capability Register" is created. My interpretation of relevant part of the PCIe standard is that in "Resizable BAR Capability Register" I should select every BAR size I allow for my Endpoint by setting '1' for the bit of the corresponding size. If I allow BAR size of 256MB and 128MB and 64 MB then the value advertised in "Resizable BAR Capability Register" should be 0x1C00. Xilinx customization of Integrated Block for PCIe allows for selecting only one value (not mentioning that it does is incorrectly, see first point) and it is in my opinion incorrect interpretation.

 

Any comments to the above are welcomed 

Regards

Wojtek

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coryb
Moderator
Moderator
948 Views
Registered: ‎02-11-2014

Hey @wojtek,

 

This is a known issue with the 7-series Integrated Block for PCIe core. I created AR70051 to document this issue. The AR will include a workaround and other information on the topic.

 

Thanks,

Cory

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