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bkeitch
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Registered: ‎11-22-2019

Is tandem loading possible in ultrascale+ ku3p?

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Is tandem loading possible with  ultrascale+ ku3p part? According to "DMA/Bridge Subsystem for PCIe v4.0" p.69 it's not, but this is from December 20, 2017 Has there been an update?

 

Vivado lets me build an example project, but I can not get it to work. Is this a bug in Vivado, or is the documentation out of date?

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miker
Xilinx Employee
Xilinx Employee
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Registered: ‎11-30-2007

@bkeitch 

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miker
Xilinx Employee
Xilinx Employee
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Registered: ‎11-30-2007

@bkeitch 

Are you referring to the DMA/Bridge Subsystem for PCI Express Product Guide (PG195; v4.1)?  Reference page 81:

forums_pg195_p81.png

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miker
Xilinx Employee
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Registered: ‎11-30-2007

@bkeitch 

Did the reply answer your question?  If so, would you please select Accept as Solution so that others may benefit from your experience.  If you found the reply helpful, please also provide a Kudos.

Please Reply, Kudos, and Accept as Solution.

View solution in original post

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