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428 Views
Registered: ‎06-30-2017

Is xdma h2c engine has a "pause" state?

hi,all
     

i have a question about xdma:

      i make h2c descriptor(not c2h) is a cycle descriptor, it mean that i don't want the engine stop when a stream finished. i want the engine at a "pause" state at this time. then when i prepare a new dma address insert the next descriptor, the engine can from the "pause" state to "run" state for process the next new desc,  don't needed to change the SGDMA Descriptor Address(contine the last finished desc address).

   How can it be achieved?

 

thanks!

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3 Replies
336 Views
Registered: ‎06-30-2017

Re: Is xdma h2c engine has a "pause" state?

Nobody knows?

i think use xdma credit register can achieve this problem?

thanks all!

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Xilinx Employee
Xilinx Employee
313 Views
Registered: ‎08-02-2007

回复: Is xdma h2c engine has a "pause" state?

have you consider parpareing the descriptor eariler and you can use the “Nxt_adr” for Address of the next descriptor in the list

engine will then fetch this info to start next stream, the next addrss can be a ring in this case but  the total number of descriptor is predefined 

 

 

 
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301 Views
Registered: ‎06-30-2017

回复: Is xdma h2c engine has a "pause" state?

thanks Liy:

According to your suggestion, the dma have fetch all the desc into fpga, but this is not my wanted. because the src or dst address i  must dynamic changed. for example:in a network driver, when a skb arrived, i must insert this skb.data dma add to the desc ,and then let's the engine continue to fetch the new desc.

use the engine the credit mode ok? when a prepare a desc, write to credit reg to 1,And so on.... 

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