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Visitor
Visitor
8,261 Views
Registered: ‎02-13-2015

Issue Simulating PCI Express IP Block

Supporting Information:

ISE Design Suite 14.7

Simulator:  ISim

OS: Windows 7

IP: Virtex-6 Integrated Block for PCI Express Version 2.5

Target Device: XC6VSX475T

Target Package: FF1759

Speed Grade: -2

 

IP Core Configuration:

Port Type: Root Port

Lane Width: x1

Link Speed: 5.0 GT/s

Interface Frequency: 125MHz

 

Issue:

When simulating the example design provided with the IP, a Simulation Timeout failure occurs.  No changes were implemented to the design and the simulation was run as described in the user manual (UG671) under Simulating the Example Design with the provided script (simulate_isim.bat).  Attached is the resulting command prompt screenshot.  The system links successfully but does not successfully configure the endpoint. I believe the simulation timeout occurs while waiting for a completion to be returned from the endpoint. I have also attached the project XCO file.

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Scholar
Scholar
8,206 Views
Registered: ‎02-03-2010

Hi,

 

It looks like this is problem with VHDL core only. The verilog based core simulaiton works fine.

 

 

Regards,

Koti Reddy

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