cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
pearliyi
Observer
Observer
966 Views
Registered: ‎10-13-2017

Issues about PS PCIe DMA reset on ZynqMP Ultrascale+

I use the PS PCIe as an Endpoint device on ZynqMP Ultrascale+.

The PS PCIe DMA is used to transfer data from a Linux PC to the board.

The transmission can work well.

But if I disable the transfer during the DMA is running, 

the next new transmission will definitely fail with more data transferred than expected.

Actually I did the DMA reset as the UG1085(V1.8) said in chapter "Disabling an Active DMA Channel" on page 861.

But the problem is still as before.

屏幕快照 2018-11-02 上午11.01.40.png

 

Does anyone meet the same issue?

I doubt the FIFO of the DMA is not flushed correctly during the reset,

is there anyway to do the flush work except reset.

Tags (2)
0 Kudos
2 Replies
deepeshm
Xilinx Employee
Xilinx Employee
908 Views
Registered: ‎08-06-2008

kvikramaxlnx
Contributor
Contributor
366 Views
Registered: ‎05-25-2018

Hi,

 

  Have you tried Egress as well, i.e PS-PCIe EP initiating transfer to x86 ??

In Service,
Kamalesh Vikramasimhan
www.yantravision.com
0 Kudos