UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer sponduri
Observer
370 Views
Registered: ‎07-31-2018

Issues with PCIe configured as root port in UltraScale MPSoC

Hi,

I am working on a custom embedded board based on xczu3cg-sfvc-784-1-i. I am trying to configure the ps-pcie module as root port x1 with 5gbps. There is an m.2 connector on the board to which one pair of gtr lines are routed and there is a clock generator on board which supplies a common clock of 100MHz for both PS GTR Bank and the end point on m.2 connector.

The clock generator is not programmed on startup and has to be programmed manually once the linux starts up. The problem is that with the clock generator programmed, I am having a kernel crash on doing an lspci (when it attempts to read the pcie configuration data). This crash would happen only when there is an endpoint plugged into the m.2 connector. If no end point there is no crash. 

Please throw some light on why this could be happening. Please guide me on debugging this issue. 

 

Thanks.

0 Kudos
3 Replies
Moderator
Moderator
330 Views
Registered: ‎02-16-2010

Re: Issues with PCIe configured as root port in UltraScale MPSoC

@sponduri

Are you applying a reset pulse after the clock is set up for PS-PCIe?

Are you using the first stage boot loader for the PS-PCIe design?

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
Observer sponduri
Observer
289 Views
Registered: ‎07-31-2018

Re: Issues with PCIe configured as root port in UltraScale MPSoC

Are you applying a reset pulse after the clock is set up for PS-PCIe?

Yes I am doing that, and

Are you using the first stage boot loader for the PS-PCIe design?

I don't understand what you meant by this. Is there a separate fsbl for PS-PCIe design? I am using the fsbl that is copied by petalinux by default into images/linux folder to generate BOOT.BIN

0 Kudos
Observer sponduri
Observer
255 Views
Registered: ‎07-31-2018

Re: Issues with PCIe configured as root port in UltraScale MPSoC

I have a followup question on the fsbl. Do I need to have any patchwork on the default fsbl code in order to configure the pcie correctly?

I am suspecting that the fsbl is not configuring the pcie and gtr configuration for pcie correctly. Any help regarding this would be very useful.

0 Kudos