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Observer
Observer
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Registered: ‎07-08-2015

Kintex-7 FPGA PCIe upstream traffic simulation

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Dear all,

I'm trying to simulate the following IP : AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8
Using Vivado v2019.1 for a kintex7 FPGA.
It creates a root port model that is made to accept upstream and downstream traffic according to the documentation. PG055.

The default example design has only an AXI slave (ram block) connected to it.

I would like to test my AXI master as well but I have no idea how to do that.
I created an master AXI traffic generator that I connected to my AXI-PCIe bridge IP.

However, when I launch the simulation, the signal s_axi_awready, s_axiwready do never get high. I suppose there should be some trick to enable incoming traffic coming from the slave AXI bus of the bridge IP.

In the following figure, the blue rectangle represents the module that I try to add to the example design.

axi_pcie.jpg

 

Could someone tell me why the s_axi_awready is never asserted to '1'?

Thanks a lot and have a great day!

axi_pcie.jpg
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Observer
Observer
181 Views
Registered: ‎07-08-2015

Re: Kintex-7 FPGA PCIe upstream traffic simulation

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I found after two days
I needed to set the bus master enable bit in my simulation files to enable transaction from the EP to RC.

board.RP.cfg_usrapp.TSK_READ_CFG_DW(32'h00000004);
board.RP.cfg_usrapp.TSK_WRITE_CFG_DW(32'h00000004, 32'h00000007, 4'b1110);
board.RP.cfg_usrapp.TSK_READ_CFG_DW(32'h00000004);

board.RP.tx_usrapp.TSK_TX_TYPE0_CONFIGURATION_WRITE(board.RP.tx_usrapp.DEFAULT_TAG,12'h04, 32'h00000007, 4'b0111);
board.RP.tx_usrapp.DEFAULT_TAG = board.RP.tx_usrapp.DEFAULT_TAG + 1;
board.RP.tx_usrapp.TSK_TX_TYPE0_CONFIGURATION_READ(board.RP.tx_usrapp.DEFAULT_TAG, 12'h04, 4'hF);
board.RP.tx_usrapp.DEFAULT_TAG = board.RP.tx_usrapp.DEFAULT_TAG + 1;

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Observer
Observer
182 Views
Registered: ‎07-08-2015

Re: Kintex-7 FPGA PCIe upstream traffic simulation

Jump to solution

I found after two days
I needed to set the bus master enable bit in my simulation files to enable transaction from the EP to RC.

board.RP.cfg_usrapp.TSK_READ_CFG_DW(32'h00000004);
board.RP.cfg_usrapp.TSK_WRITE_CFG_DW(32'h00000004, 32'h00000007, 4'b1110);
board.RP.cfg_usrapp.TSK_READ_CFG_DW(32'h00000004);

board.RP.tx_usrapp.TSK_TX_TYPE0_CONFIGURATION_WRITE(board.RP.tx_usrapp.DEFAULT_TAG,12'h04, 32'h00000007, 4'b0111);
board.RP.tx_usrapp.DEFAULT_TAG = board.RP.tx_usrapp.DEFAULT_TAG + 1;
board.RP.tx_usrapp.TSK_TX_TYPE0_CONFIGURATION_READ(board.RP.tx_usrapp.DEFAULT_TAG, 12'h04, 4'hF);
board.RP.tx_usrapp.DEFAULT_TAG = board.RP.tx_usrapp.DEFAULT_TAG + 1;

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