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Contributor
Contributor
249 Views
Registered: ‎05-22-2018

MGT pin mismatch for DMA PCIe IP

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Dear All,

As per the ASCII pinout file is of XCZU21DR-FFVD1156 the following pins are :

C32 MGTYRXN0_131 
B34 MGTYRXN1_131 
B30 MGTYRXN2_131 
A32 MGTYRXN3_131 
C31 MGTYRXP0_131 
B33 MGTYRXP1_131 
B29 MGTYRXP2_131 
A31 MGTYRXP3_131 
D25 MGTYTXN0_131 
C27 MGTYTXN1_131 
B25 MGTYTXN2_131 
A27 MGTYTXN3_131 
D24 MGTYTXP0_131 
C26 MGTYTXP1_131 
B24 MGTYTXP2_131 
A26 MGTYTXP3_131

But while configuring the DMA PCIe IP (ver 4.1) with same MGTY_131  in Vivado (2018.2), the IO planner window is showing reverse assignment (snapshot attached). I am sure I am missing something here. Please help.

Capture.PNG

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Xilinx Employee
Xilinx Employee
178 Views
Registered: ‎10-19-2011

Re: MGT pin mismatch for DMA PCIe IP

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Hi @vparashar ,

the naming of the transceiver locations in the package and the bus naming in the IP are two different things. The IP just connects it so that it looks swapped when you look at it this way.

The IP actually supports a lane swap. So it would not matter if you connect with [3:0] or [0:3].

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1 Reply
Highlighted
Xilinx Employee
Xilinx Employee
179 Views
Registered: ‎10-19-2011

Re: MGT pin mismatch for DMA PCIe IP

Jump to solution

Hi @vparashar ,

the naming of the transceiver locations in the package and the bus naming in the IP are two different things. The IP just connects it so that it looks swapped when you look at it this way.

The IP actually supports a lane swap. So it would not matter if you connect with [3:0] or [0:3].

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------