UPGRADE YOUR BROWSER
We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
09-11-2019 03:29 AM
Dear All,
As per the ASCII pinout file is of XCZU21DR-FFVD1156 the following pins are :
C32 MGTYRXN0_131
B34 MGTYRXN1_131
B30 MGTYRXN2_131
A32 MGTYRXN3_131
C31 MGTYRXP0_131
B33 MGTYRXP1_131
B29 MGTYRXP2_131
A31 MGTYRXP3_131
D25 MGTYTXN0_131
C27 MGTYTXN1_131
B25 MGTYTXN2_131
A27 MGTYTXN3_131
D24 MGTYTXP0_131
C26 MGTYTXP1_131
B24 MGTYTXP2_131
A26 MGTYTXP3_131
But while configuring the DMA PCIe IP (ver 4.1) with same MGTY_131 in Vivado (2018.2), the IO planner window is showing reverse assignment (snapshot attached). I am sure I am missing something here. Please help.
09-19-2019 03:59 AM
Hi @vparashar ,
the naming of the transceiver locations in the package and the bus naming in the IP are two different things. The IP just connects it so that it looks swapped when you look at it this way.
The IP actually supports a lane swap. So it would not matter if you connect with [3:0] or [0:3].
09-19-2019 03:59 AM
Hi @vparashar ,
the naming of the transceiver locations in the package and the bus naming in the IP are two different things. The IP just connects it so that it looks swapped when you look at it this way.
The IP actually supports a lane swap. So it would not matter if you connect with [3:0] or [0:3].