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mengmcxl
Participant
Participant
585 Views
Registered: ‎07-16-2019

MPSOC PS PCIe EP DMA register access issue

Hi,

I use ZCU102 MPSOC PS PCIe EP DMA. The host can access the DMA registers with BAR0. But PS cannot access the DMA registers. I see the DREG is 0 somehow. It should be non-zero. Here is more detail:

 

We are using Zcu102 as PCIE Endpoint and Xeon COMe main PC as Root point.

     In COMe root complex side, we can use “lspci” find PCIE bus address map and can expected results for AXI_PCIE_DMA Register following below:

https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.htmlhttps://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html

 

 

But in FPGA side:

All of these registers’ values are all 0  and can’t be written by memory utility.

./devmem2 0xfd0f007c w  

         00000000    ----- expected 00008000

./devmem2 0xfd0f00fc w

         00000000    ----- expected 00008010

  ./devmem2 0xfd0f0050 w

         00000000

  ./devmem2 0xfd0f0050 w 0x5555

          DMA_CHANNEL_SCRATCH0 (AXIPCIE_DMA) Register --0xFD0F0050 is a rw register and it should be written as value 0x5555

./devmem2 0xfd0f0050 w

        00000000    ----- expected 00005555

 

Ho can we get the expected results in this zcu102 PCIE endpoint? 

 

Thanks

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2 Replies
garethc
Moderator
Moderator
470 Views
Registered: ‎06-29-2011

Hi @mengmcxl 

The ZCU102 board will not work as a PCIe Endpoint due to two main reasons:

1. The ZCU102 card provides a PCIe reference clock and puts it on the PCIe connector. This is incompatible when trying to be an EP as the host will be providing the reference clock.
2. The level shifter for #PERST is an output and not an input as would need to be for an EP.

Thanks,

Gareth


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355 Views
Registered: ‎09-20-2019

I have the same issue, I also opened a new thread:

https://forums.xilinx.com/t5/PCIe-and-CPM/PCIe-Address-Translation-RunTime-Configuration/m-p/1087594

My board is properly configured as endpoint, it works properly, I only need to runtime pass a parameter from windows host to the ultrascale+ endpoint. I'm able to read and write DMA_CHANNEL_SCRATCH0 register from windows driver but I can't access from PS Zynq code.

Could you help me?

Nicola

 

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