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Visitor
Visitor
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Registered: ‎09-16-2009

The MSI-X saga so far:

 

This code is being written in Fedora 12 Linux. The V6 project is a modified UG1052 project.

 

MSI works- cfg_interrupt_n apparently triggers a MWr TLP with the address and data below.

 

************** portion of lspci -vvv with MSI enabled, MSIX disabled  *********************

    Capabilities: [48] MSI: Enable+ Count=1/8 Maskable- 64bit+
        Address: 00000000feeff00c  Data: 4182

**********************************************************************************************

 

UG517 states that "MSI-X interrupts must be generated by the user by composing MWr TLPs on the TRN Tx interface; Do not use the cfg_interrupt interface."

 

************** portion of lspci -vvv with MSI disabled, MSIX enabled  *********************

Capabilities: [48] MSI: Enable- Count=1/8 Maskable- 64bit+
        Address: 00000000feeff00c  Data: 4   

Capabilities: [9c] MSI-X: Enable+ Count=8 Masked-
        Vector table: BAR=1 offset=00000000
        PBA: BAR=2 offset=00000000

********** BAR1 contents ******************

low addr  high addr   message  control

feeff00c 00000000 0000418a 00000000
feeff00c 00000000 00004192 00000000
feeff00c 00000000 0000419a 00000000
feeff00c 00000000 000041a2 00000000
feeff00c 00000000 000041aa 00000000
feeff00c 00000000 000041b2 00000000
feeff00c 00000000 000041ba 00000000

*********************************************

 

BAR1 is the MSI-X Table, BAR2 is the PBA Array. BAR1 contents indicate that the proper info is available for transmission via a MWr TLP, but sending the MWr TLP does not trigger the interrupt.

 

The MWr TLP is formatted exactly like a 4 byte message MWr TLP from the UG1052 DMA. PDFs of the DMA and the subsequent MWr TLP attempting to trigger the MSI-X interrupt are attached.

 

The next test will be to try to trigger MSI with a MWr TLP rather than using the cfg_interrupt interface.

 

If you have successfully implemented MSI-X in Linux, any clues as to why the interrupt is not triggering would be deeply appreciated.

 

 

 

 

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Visitor
Visitor
8,980 Views
Registered: ‎09-16-2009

// what we see for MSI MWr TLP:
// 40000001 0800000b
// feeff00c e9410000
// from lspci -vvv:
// Capabilities: [48] MSI: Enable+ Count=1/8 Maskable- 64bit+
// Address: 00000000feeff00c Data: 41e9

 

so I think I answered my question...

 


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Visitor
Visitor
7,426 Views
Registered: ‎09-16-2009

and this...

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Visitor
Visitor
7,414 Views
Registered: ‎09-16-2009

I am going to put chipscope on the physical interface and see what MSI sends for MWr TLPs, that should anwer the question. I will post what I find.

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Visitor
Visitor
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Registered: ‎09-16-2009

// what we see for MSI MWr TLP:
// 40000001 0800000b
// feeff00c e9410000
// from lspci -vvv:
// Capabilities: [48] MSI: Enable+ Count=1/8 Maskable- 64bit+
// Address: 00000000feeff00c Data: 41e9

 

so I think I answered my question...

 


View solution in original post

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