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Teacher
Teacher
6,389 Views
Registered: ‎11-14-2011

MSI multiple vectors

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Hello,

 

Following on from this thread, are there any obvious options to allow the PCIe-PLB Bridge IP in XPS (any version, I currently use v4.06a) to easily handle multiple MSI vectors (i.e. as part of the generated IP rather than some hack that I would have to implement) in Spartan 6?

 

I read that there is the potential to handle 32 separate vectors (from the PCIe Endpoint UG654: cfg_interrupt_mmenable[2:0] = 0b101), which would be very nice indeed ..

 

Thanks,

 

Howard

 

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"That which we must learn to do, we learn by doing." - Aristotle
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Xilinx Employee
Xilinx Employee
9,973 Views
Registered: ‎08-06-2008

Hi,

 

MSI Multiple Vectors is not supported in the plbv46 version of the PCIe core. You might be able to get it to work with some hack as you mentioned. However, that is not something that has been tested and of course will not be supported from the Xilinx Official Support standpoint. You might want to switch to the axi version of the core. All new features in future will go into this core. No ehancements will be done in the plbv46 pcie core.

 

Thanks,

DMS

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Xilinx Employee
Xilinx Employee
9,974 Views
Registered: ‎08-06-2008

Hi,

 

MSI Multiple Vectors is not supported in the plbv46 version of the PCIe core. You might be able to get it to work with some hack as you mentioned. However, that is not something that has been tested and of course will not be supported from the Xilinx Official Support standpoint. You might want to switch to the axi version of the core. All new features in future will go into this core. No ehancements will be done in the plbv46 pcie core.

 

Thanks,

DMS

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