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Observer
Observer
7,215 Views
Registered: ‎12-18-2009

Making PCIe Registers

Hi,

I am newbie in PCIe design, I am targeting virtex-5 FPGA with ISE 11.4. I have created an endpoint core which has two BARs, both of which are of 32 bit and 8K. I can access these bars in PCI tree. Now I want to make some registers (which can be accessed by PC drivers ) to pass some information like starting DMA , its address, no of TLPs etc

 

I want to ask how to do this? Should I use these BARS (which I have made while creating the Endpoint core) ? Or there is some other way of making registers which uses Block RAM etc?

 

I have seen the implementation of Bus Master DMA Performance Demonstration (XAPP1052)  but its does not use any BRAM for making registers. Actually it uses some conditions in case statement that transfer data? (I am not sure about it)

 

Can any body give me some idea or some good references for it?

I would be very grateful for that

 

Regards,

Sadiqhus

Message Edited by sadiqhus on 04-19-2010 08:16 AM
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7 Replies
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Xilinx Employee
Xilinx Employee
7,208 Views
Registered: ‎09-02-2009

Hi Sadiqhus,

 

A typical application would implement control items such as address and size in registers and the data itself in BRAM.  While it is possible to store this control information in BRAM, it complicates the design as you will need to control the address lines of the BRAM to read the different control values as they are needed.

 

If you do need to use BRAM though, this can be done.  I would suggest using the BRAM in dual port mode where one port is writing data from the PCIe block into the BRAM and the other port is reading the control registers.  This might save you the complexity of having to multiplex between reading and writing the control information.

 

Jason

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Observer
Observer
7,203 Views
Registered: ‎12-18-2009

Hi Jason,

 

thanks a lot for your quick reply,

 

1- I think I would need both registers as well as BRAM.

Would you please explain the process of making registers which are accessible from both sides in case I don't want to use BARs which are formed during end block core making?

 

2- Your suggestion about dual port BRAM seems great. I have used BRAM in dual port mode earlier but tell me one thing,  as you said "one port is writing data from the PCIe block into the BRAM " how to map one side to PCIe so that it can be accessed by Driver running on PC side? Please explain it a little.

 

 

Thanks and Best Regards,

sadiqhus

 

 

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Xilinx Employee
Xilinx Employee
7,183 Views
Registered: ‎09-02-2009

Hi Sadiqhus,

 

The designs that I have seen typically have two BARs.  One for the control of the DMA and one for the data of the DMA.  The BAR hit signal can then be used to mux between the control path and the data path logic.

 

As for the BRAM, you can map the BRAM to a BAR.  So when your software driver read/writes from that particular BAR in the device, you will know that it is reading/writing the BRAM (or blocks of BRAM).  Simliarly, the software should know which BAR is the control BAR and can read/write those registers that are implemented as flops.

 

Jason

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Observer
Observer
7,165 Views
Registered: ‎12-18-2009

Hi Jason,

 

Can you please explain the method of implementing this "Mapping"  ( of BAR to BRAM) on FPGA side ? I would be very grateful to you for this.

 

 

Thanks and Best Regards,

sadiqhus

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Observer
Observer
7,109 Views
Registered: ‎12-18-2009

Hi,

 

Still waiting for any hint! Can any body help?

 

Thanks and Best Regards,

Sadiqhus

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Xilinx Employee
Xilinx Employee
7,095 Views
Registered: ‎09-02-2009

Hi Sadiqhus,

 

The easiest way to do this is to create a loadable counter.  The size of the counter will be determined by the size of the BAR.  For example, a 4Kb BAR requires 12-bits.  Because PCIe transactions are Dword aligned though, the lowest two bits are always 0.  So the counter becomes a 10-bit loadable counter.

 

When the trasaction comes in, and the BAR HIT is asserted, load address[11:2] into the 10-bit loadable counter.  The new address for your BRAM is now {counter[9:0], 2'b00} which covers your 4Kb of space.  The counter can now be incremented based on the size of the read or write.

 

Note that this is for a 32-bit data bus.  If you have a 64-bit data bus, the counter will be one less bit and the bottom 3-bits are always zero.  The application will need to take care to start transaction quad word aligned, or you will need to add logic to address this in hardware.

 

Hope this helps.

 

Jason

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Newbie
Newbie
6,945 Views
Registered: ‎05-09-2010

Hi  sadiqhus:

 

I'm a new to design a PCIe driver.  Now i  have a problem with implementing DMA transfer from the PCIe endpoint into the computer, i don't  kown the DMA registers address, and don't kown  how to set the registers ,  though i have read the document PCI Express® Base Specification Revision 2.1.

 

would you please  tell me the address of the registers for DMA in Pcie Virtex-5 and how to set that for DMA?

 

Thanks and Regards,

shake

 

 

 

 

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