12-05-2018 11:00 PM
We are developing a system with a custom processor, Microblaze and some peripherals in VC709 FPGA using Xilinx Vivado. We are using two 'PCIe : BARs' in 'AXI Bridge for PCI express gen 3'.
The changes we make in the block configuration of the PCI express block are not getting reflected on the host side.
For example, when we set the BAR0 for 2GB and BAR1 for 2MB, we get two regions of 4KB and 4MB. And this doesn't change when we tried varying different BAR combinations.
$lspci -vv 0a:00.0 Memory controller: Xilinx Corporation Device 7038 Subsystem: Xilinx Corporation Device 0007 Physical Slot: 3 Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin A routed to IRQ 16 Region 0: Memory at fbff0000 (32-bit, non-prefetchable) [size=4K] Region 1: Memory at fb800000 (32-bit, non-prefetchable) [size=4M] Capabilities: <access denied> Kernel modules: riffa
Could somebody explain this behavior? Is it related to the OS handling of PCIe peripherals?
12-05-2018 11:30 PM
this is not expeted
which version of vivado are you using？
you can check the BAR size in the IP source file to check if the correct value is writen to
12-14-2018 09:50 PM
(Q) Where can I find the IP source file?
Solution to my first question
I have been using Xilinx SDK for programming the FPGA. But it the SDK was always loading an old bit stream. I have solved it by programming the FPGA through Vivado itself.
Tools > Xilinx hardware manager > open target > autoconnect > program device
Credits: Mandar Datar (HPC Lab, Dept of EE, IIT Bombay)