cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
tonyle
Contributor
Contributor
882 Views
Registered: ‎10-01-2010

Mapping a 32-bit PCI-Express BAR above the 4GB boundary

Hi all,

I am instantiating the DMA/Bridge Subsystem for PCI Express in Virtex UltraScale+ using IP Integrator. Our design has a local 37-bit (128 GB) address space, and I've set the core's AXI address width to 37 bits in IP Integrator. I am trying to map a 32-bit PCIe BAR to location 0x1000000000 (64 GB). When I try to do this, I get an out-of-range error:

Mapping a 32-bit BAR at 64 GBMapping a 32-bit BAR at 64 GB

I'd supposed this was because I was trying to assign a 32-bit BAR above the 4 GB boundary. However, IP Integrator has no problem mapping this BAR to 0x400000000 (16 GB), and validate_bd_design does not flag an error on this setting:

Mapping a 32-bit BAR at 16 GBMapping a 32-bit BAR at 16 GBIs there any way I can get this BAR to map to my desired location?

Tags (1)
0 Kudos
3 Replies
kurihara
Xilinx Employee
Xilinx Employee
816 Views
Registered: ‎07-26-2012

What is the version of Vivado? If it is not 2019.1, please try the latest one.

0 Kudos
tonyle
Contributor
Contributor
800 Views
Registered: ‎10-01-2010

We are indeed using 2019.1.

0 Kudos
kurihara
Xilinx Employee
Xilinx Employee
764 Views
Registered: ‎07-26-2012

If AXI bus width is 64 bits, the address is accepted in GUI. Therefore, I think this is a GUI problem.

At this point could you try following steps?

1) After synthesizing the design and find the xdma from the netlist and select it.

2) In tcl console, type the following command :

set_property C_PCIEBAR2AXIBAR_0 64'h0000001000000000 [get_selected_objects ]

3) Save and Implement the design

4) Open Implemented design and check the expected property still exist in it.

0 Kudos