Current User Logic interface is TRN, I want to migrate to AXI4-ST Enhanced as in the IP core generated by Vivado 2013.4.
Is there any step-by-step migration like what it used be in UG671?
I don't think the migration will be easy.
However, we want to minimize the efforts of migration since we don't need any functionality upgrade.
I searched through Xilinx: only PG023 is provided and does not contain any step-by-step migration.
AXI4-ST enhanced is dramatically different from AXI4-ST Basic and TRN.
Any advice, guys?
Gen3 core has different kind of client interface which handles the requests and replies on seperate axi interfaces.
So apart from TRN-AXI bridge there should be logic which transfers the packets from trn to AXI-ST od Requestor and completer respectively.
thesre is no such migration guide.