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jmantzouranis
Visitor
Visitor
910 Views
Registered: ‎02-04-2019

Minimum Latency of QDMA subsystem for PCIe

Hi all,

What is the minimum latency for a 300-byte packet, for instance, using the QDMA subsystem for PCIe, from host to FPGA (VU9P)? There only seem to be measurements and documentation related to throughput.

 

https://www.xilinx.com/products/intellectual-property/pcie-qdma.html

https://www.xilinx.com/Attachment/Xilinx_Answer_71453_QDMA_Performance_v6.pdf

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4 Replies
kurihara
Xilinx Employee
Xilinx Employee
833 Views
Registered: ‎07-26-2012

If it is the minimum value, I recommend measurement by simulation. In actual measurement, it is difficult to trigger the start point and end point, and the environment of the platform has an effect.

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liy
Xilinx Employee
Xilinx Employee
800 Views
Registered: ‎08-02-2007

There is a way to measure the latency in the file you mentioned
https://www.xilinx.com/Attachment/Xilinx_Answer_71453_QDMA_Performance_v6.pdf

please check chapter Latency Measurements

 

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jmantzouranis
Visitor
Visitor
709 Views
Registered: ‎02-04-2019

Has anyone measured this and have an approximate/ballpark value?
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vconst89
Adventurer
Adventurer
423 Views
Registered: ‎09-10-2020

Hi,

The question is still open. @liy @kurihara , is it possible to ask Xilinx to publish a latency measurement report?

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