12-17-2019 08:20 AM - edited 12-17-2019 08:21 AM
What is the minimum latency for a 300-byte packet, for instance, using the QDMA subsystem for PCIe, from host to FPGA (VU9P)? There only seem to be measurements and documentation related to throughput.
12-19-2019 05:53 PM
If it is the minimum value, I recommend measurement by simulation. In actual measurement, it is difficult to trigger the start point and end point, and the environment of the platform has an effect.
12-26-2019 11:55 PM
There is a way to measure the latency in the file you mentioned
please check chapter Latency Measurements