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mike.mandeville
Contributor
Contributor
683 Views
Registered: ‎06-27-2017

Missing Document/example file

I'm looking for the associated document/user guide/example for this AR 72076 that seems unavailable now.

https://www.xilinx.com/support/answers/72076.html

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6 Replies
djj
Visitor
Visitor
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Registered: ‎01-09-2019

I'm also looking for this documentation. Is it available anywhere else?

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garethc
Moderator
Moderator
644 Views
Registered: ‎06-29-2011

Hi @mike.mandeville 

Please find attached the document. Note that this AR:72076 has been taking down as we are actively updating it as there are some changes required and an update with the most recent tools. So the attached document requires some changes but you can use it as a guide and it should work with some little extra effort.

For example some changes required:
*******************************************************************************************************

    1. Adding IP "Zynq UltraScale+ MPSoC" is missing
    2. Instruction says to add only a "System ILA". But following figures say there should be 2 "System ILA".
    3. Figure 32 : Re-customize IP "Zynq UltraScale+ MPSoC" -> PS-PL Configuration -> General -> Address Fragmentation -> There is NO "High Address"
    4. Re-customize IP "Utility Vector Logic" -> C_SIZE should be set "1". (Default value is 8 and it makes bitstream write error.)
    5. Figure 56 explains connection with "system_ila_0" and "heart_beat_0" but no instruction for both of them is found.
    6. Figure 57 explains all connection between all aresetn/resetn port in axi_interconnect_0/1, system_ila_0/1. But no instruction for axi_interconnect_0 and system_ila_0 is found. Additionally, xdma_0:axi_aresetn should be included in this connection(According to Figure 62) but not explained.

*******************************************************************************************************

Thanks,

Gareth


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garethc
Moderator
Moderator
642 Views
Registered: ‎06-29-2011

Hi @djj 

I have attached it to my reply to @mike.mandeville . Please note my comments about it and that it is currently being updated but you can use this version for now.

Thanks,

Gareth


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djj
Visitor
Visitor
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Registered: ‎01-09-2019

Noted, thanks. Are the example source files available also?

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garethc
Moderator
Moderator
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Registered: ‎06-29-2011

@mike.mandeville @djj 

Adding example source files.

Thanks,

Gareth


------------------------------------------------------------------------------------------------

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If starting with Versal take a look at our Versal Design Process Hub and our
Versal Blogs

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JoaoGarrido
Visitor
Visitor
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Registered: ‎04-07-2021

Hi,

Followed the guide to create a PS endpoint on a ZCU106 (the UltraZed example) but, although I can communicate with the board through the serial terminal, the PCIe link is down and the board isn't detected on the PC (tried 2 different PC: a B450M S2H and HP 3397) running $ lspci or $ dmesg.
Running Vivado 2020.2 and Vitis 2020.2.


Also tried several example designs with PCIe endpoint IP and DMA PCIe Subsystem IP. Neither were detected by the PC.

How should I proceed?

Thanks for the support provided,

Joao Garrido

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