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Visitor wraoglter
Visitor
194 Views
Registered: ‎05-16-2018

Multi-Descriptor of QDMA

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Hi all,

I tried to integrate the QDMA IP with my PCIe Root Port IP and simulate this design together.

As following:  MY_RP pipe interface-- QDMA pipe interface and here are my steps:

  1. To export the simulation of the QDMA sub-system example on Xilinx 2019.1.
    (pg302-qdma.pdf Ch6 Example Design: AXI Memory Mapped and AXI4-Stream With   Completion Dafault Example Design)
  2. To replace Xilinx's RootPort with my RootPort IP, and connected the both IP by pipe inferface.
  3. To sent a serial of PCIe transaction and this simulation can finish the PCIe enumeration. 
    EP: func_1_0_0(EP, type0, single-f): vendor_id 10ee, device_id 9038
    | bar0(64bit, MEM, NonPref , base cf00000, len 20000)
    | bar2(64bit, MEM, NonPref , base cf20000, len 1000)
  4. To duplicate your steps on example to testing QDMA (usp_pci_exp_usrapp_tx.v).

Now I encounter an issue. When I tested the MM-H2C traffic with single queue and multi-descriptors, it hang when I configure the Descriptor numbers great than 14 (ex:15). But it can pass when descriptor number as 1~14. From my trace log, I saw QDMA only sent MRDs for fetching 14 descriptors and stay on idle after it finished those 14 descriptors. Also it doesn't sent the Writeback Status to RootPort. I am not sure whether this issue is caused by my wrong configured or not. 


As attached trace log file (pass_14.log). I put the descriptor address form offset 0 of RC's bar domain, ex: desc[0]: 0x0, desc[1]: 0x20 ... desc[13]: 0x1A0, and dma_len is always 128byte on each descriptor and data offset is from 0x400, 0x480, 0x500 ....  of RC's Bar.

XXX_INF: @82150.003ns : Step MM H2C.1a: 0, desc_addr= 'h0, src_addr(Host)= 'h400, dst_addr(Card)= 'h0, dma_length= 128 Bytes 
XXX_INF: @82150.003ns : TASK QDMA MM H2C DSC at rc_mbar_base 'hf301900000000000, offset 'h0000000000000000 
XXX_INF: @82150.003ns : Generate Descriptor data (QDMA Descriptor content) 
XXX_INF: @82150.003ns : MM H2C Mapping DATA_STORE to RC mem space for QDMA Descriptor 
 Desc[0] rc.set_mem_dwords['hf301900000000000] = 'h00000400
 Desc[0] rc.set_mem_dwords['hf301900000000004] = 'hf3019000
 Desc[0] rc.set_mem_dwords['hf301900000000008] = 'h40000080
 Desc[0] rc.set_mem_dwords['hf30190000000000c] = 'h00000000
 Desc[0] rc.set_mem_dwords['hf301900000000010] = 'h00000000
 Desc[0] rc.set_mem_dwords['hf301900000000014] = 'h00000000
 Desc[0] rc.set_mem_dwords['hf301900000000018] = 'h00000000
 Desc[0] rc.set_mem_dwords['hf30190000000001c] = 'h00000000

 

I also print my configure of QDMA on trace file. Step MM-H2C.2: Setup the Descriptor engin as following: (pid is 'h000e on Register 'h804)

XXX_INF: @85266.002ns : Write Data to QDMA BAR at address 'h804 with data 'h0000000e Done 
XXX_INF: @85366.002ns : Write Data to QDMA BAR at address 'h808 with data 'h80121005 Done 
XXX_INF: @85466.002ns : Write Data to QDMA BAR at address 'h80c with data 'h00000000 Done 
XXX_INF: @85566.002ns : Write Data to QDMA BAR at address 'h810 with data 'hf3019000 Done 
XXX_INF: @85666.002ns : Write Data to QDMA BAR at address 'h814 with data 'h00000001 Done 
XXX_INF: @85766.002ns : Write Data to QDMA BAR at address 'h818 with data 'h00000000 Done 
XXX_INF: @85866.002ns : Write Data to QDMA BAR at address 'h81c with data 'h00000000 Done 
XXX_INF: @85966.002ns : Write Data to QDMA BAR at address 'h820 with data 'h00000000 Done 
XXX_INF: @86066.002ns : Write Data to QDMA BAR at address 'h844 with data 'h00000022 Done 

You can noticed on Step MM-H2C.4, RC recevied MRD for 14 descriptor context after I wrote the number of pidx credits to the AXI-MM H2C PIDX direct address 0x18004. queue 0

XXX_INF: @86266.002ns : Write Data to QDMA BAR at address 'h18004 with data 'h0000000e Done 
XXX_INF: @86342.003ns : RC received read_mem_cb: ADDR 'hf301900000000000, NDW 'h20, FBE 'hf, LBE 'hf 
XXX_INF: @86342.003ns : RC received read_mem_cb: ADDR 'hf301900000000080, NDW 'h20, FBE 'hf, LBE 'hf 
XXX_INF: @86342.003ns : RC received read_mem_cb: ADDR 'hf301900000000100, NDW 'h20, FBE 'hf, LBE 'hf 
XXX_INF: @86342.003ns : RC received read_mem_cb: ADDR 'hf301900000000180, NDW 'h10, FBE 'hf, LBE 'hf 

Then, QDMA will send MRDs for DMA transaction, as following...  

XXX_INF: @86706.003ns : RC received read_mem_cb: ADDR 'hf301900000000400, NDW 'h20, FBE 'hf, LBE 'hf 
XXX_INF: @86722.003ns : RC received read_mem_cb: ADDR 'hf301900000000480, NDW 'h20, FBE 'hf, LBE 'hf 
XXX_INF: @86730.003ns : RC received read_mem_cb: ADDR 'hf301900000000500, NDW 'h20, FBE 'hf, LBE 'hf 
XXX_INF: @86742.003ns : RC received read_mem_cb: ADDR 'hf301900000000580, NDW 'h20, FBE 'hf, LBE 'hf 
XXX_INF: @86754.003ns : RC received read_mem_cb: ADDR 'hf301900000000600, NDW 'h20, FBE 'hf, LBE 'hf 
XXX_INF: @86766.003ns : RC received read_mem_cb: ADDR 'hf301900000000680, NDW 'h20, FBE 'hf, LBE 'hf 
XXX_INF: @86778.003ns : RC received read_mem_cb: ADDR 'hf301900000000700, NDW 'h20, FBE 'hf, LBE 'hf 
XXX_INF: @86790.003ns : RC received read_mem_cb: ADDR 'hf301900000000780, NDW 'h20, FBE 'hf, LBE 'hf 
XXX_INF: @86802.003ns : RC received read_mem_cb: ADDR 'hf301900000000800, NDW 'h20, FBE 'hf, LBE 'hf 
XXX_INF: @86814.003ns : RC received read_mem_cb: ADDR 'hf301900000000880, NDW 'h20, FBE 'hf, LBE 'hf 
XXX_INF: @86826.003ns : RC received read_mem_cb: ADDR 'hf301900000000900, NDW 'h20, FBE 'hf, LBE 'hf 
XXX_INF: @86838.003ns : RC received read_mem_cb: ADDR 'hf301900000000980, NDW 'h20, FBE 'hf, LBE 'hf 
XXX_INF: @86850.003ns : RC received read_mem_cb: ADDR 'hf301900000000a00, NDW 'h20, FBE 'hf, LBE 'hf 
XXX_INF: @86866.003ns : RC received read_mem_cb: ADDR 'hf301900000000a80, NDW 'h20, FBE 'hf, LBE 'hf 

At laston Step MM-H2C.5: Check QDMA status, we will check Writeback status, as following... the pid = cid = 14 ('he)

XXX_INF: @87446.003ns : RC received write_mem_cb: ADDR 'hf3019000000001e0, FBE f, LBE f, payload_size= 2 
XXX_INF: @87446.003ns :               DATA[0] 'h000e0000 
XXX_INF: @87446.003ns :               DATA[1] 'h0000000e 
XXX_INF: @87446.003ns : AVY_WAIT_CB got expect MWR callback, addr 'hf3019000000001e0

 


On fail_15.log, I setup the 15 Descriptors and configure the pid of Register as 15 (addr 0x804) and also configure the pidx as 15 (addr 0x18004) 
But QDMA have not generate any MRD to RootPort for fetching the Descriptors. as following

...
AVY_INF: @85066.002ns : Write Data to QDMA BAR at address 'h83c with data 'hffffffff Done AVY_INF: @85166.002ns : Write Data to QDMA BAR at address 'h840 with data 'hffffffff Done AVY_INF: @85266.002ns : Write Data to QDMA BAR at address 'h804 with data 'h0000000f Done AVY_INF: @85366.002ns : Write Data to QDMA BAR at address 'h808 with data 'h80121005 Done AVY_INF: @85466.002ns : Write Data to QDMA BAR at address 'h80c with data 'h00000000 Done AVY_INF: @85566.002ns : Write Data to QDMA BAR at address 'h810 with data 'hf3019000 Done AVY_INF: @85666.002ns : Write Data to QDMA BAR at address 'h814 with data 'h00000001 Done AVY_INF: @85766.002ns : Write Data to QDMA BAR at address 'h818 with data 'h00000000 Done AVY_INF: @85866.002ns : Write Data to QDMA BAR at address 'h81c with data 'h00000000 Done AVY_INF: @85966.002ns : Write Data to QDMA BAR at address 'h820 with data 'h00000000 Done AVY_INF: @86066.002ns : Write Data to QDMA BAR at address 'h844 with data 'h00000022 Done APCI_STEP: Step MM-H2C.3: Start DMA tranfer (@86066.002ns) AVY_INF: @86166.002ns : Write Data to QDMA BAR at address 'h1204 with data 'h00000001 Done APCI_STEP: Step MM-H2C.4: Compare Data Payload (@86166.002ns) AVY_INF: @86266.002ns : Write Data to QDMA BAR at address 'h18004 with data 'h0000000f Done ...^CSimulation interrupted at 169156 NS + 2 xcelium> exit AVY_INF: rc@169156.000ns : TX buffers are empty

On fail_15_2.log, I assume my configuration may be wrong. So I modyfy the pid of Register as 15-1=14 (addr 0x804) and configure the pidx as 15 (addr 0x18004).
I saw QDMA only sent MRD for fetching 14 descriptors and stay on idle after it finished those 14 descriptors.  And we also do not receive any Writeback status.
I read MM Debug Register, the status is on idle and cmd fifo is empty too.

...
AVY_INF: @85166.002ns : Write Data to QDMA BAR at address 'h840 with data 'hffffffff Done 
AVY_INF: @85266.002ns : Write Data to QDMA BAR at address 'h804 with data 'h0000000e Done 
AVY_INF: @85366.002ns : Write Data to QDMA BAR at address 'h808 with data 'h80121005 Done 
AVY_INF: @85466.002ns : Write Data to QDMA BAR at address 'h80c with data 'h00000000 Done 
AVY_INF: @85566.002ns : Write Data to QDMA BAR at address 'h810 with data 'hf3019000 Done 
AVY_INF: @85666.002ns : Write Data to QDMA BAR at address 'h814 with data 'h00000001 Done 
AVY_INF: @85766.002ns : Write Data to QDMA BAR at address 'h818 with data 'h00000000 Done 
AVY_INF: @85866.002ns : Write Data to QDMA BAR at address 'h81c with data 'h00000000 Done 
AVY_INF: @85966.002ns : Write Data to QDMA BAR at address 'h820 with data 'h00000000 Done 
AVY_INF: @86066.002ns : Write Data to QDMA BAR at address 'h844 with data 'h00000022 Done 
APCI_STEP: Step MM-H2C.3: Start DMA tranfer (@86066.002ns)

AVY_INF: @86166.002ns : Write Data to QDMA BAR at address 'h1204 with data 'h00000001 Done 
APCI_STEP: Step MM-H2C.4: Compare Data Payload (@86166.002ns)

AVY_INF: @86266.002ns : Write Data to QDMA BAR at address 'h18004 with data 'h0000000f Done 
AVY_INF: @86342.003ns : RC received read_mem_cb: ADDR 'hf301900000000000, NDW 'h20, FBE 'hf, LBE 'hf 
AVY_INF: @86342.003ns : RC received read_mem_cb: ADDR 'hf301900000000080, NDW 'h20, FBE 'hf, LBE 'hf 
AVY_INF: @86342.003ns : RC received read_mem_cb: ADDR 'hf301900000000100, NDW 'h20, FBE 'hf, LBE 'hf 
AVY_INF: @86342.003ns : RC received read_mem_cb: ADDR 'hf301900000000180, NDW 'h10, FBE 'hf, LBE 'hf 
AVY_INF: @86706.003ns : RC received read_mem_cb: ADDR 'hf301900000000400, NDW 'h20, FBE 'hf, LBE 'hf 
AVY_INF: @86722.003ns : RC received read_mem_cb: ADDR 'hf301900000000480, NDW 'h20, FBE 'hf, LBE 'hf 
AVY_INF: @86730.003ns : RC received read_mem_cb: ADDR 'hf301900000000500, NDW 'h20, FBE 'hf, LBE 'hf 
AVY_INF: @86742.003ns : RC received read_mem_cb: ADDR 'hf301900000000580, NDW 'h20, FBE 'hf, LBE 'hf 
AVY_INF: @86754.003ns : RC received read_mem_cb: ADDR 'hf301900000000600, NDW 'h20, FBE 'hf, LBE 'hf 
AVY_INF: @86766.003ns : RC received read_mem_cb: ADDR 'hf301900000000680, NDW 'h20, FBE 'hf, LBE 'hf 
AVY_INF: @86778.003ns : RC received read_mem_cb: ADDR 'hf301900000000700, NDW 'h20, FBE 'hf, LBE 'hf 
AVY_INF: @86790.003ns : RC received read_mem_cb: ADDR 'hf301900000000780, NDW 'h20, FBE 'hf, LBE 'hf 
AVY_INF: @86802.003ns : RC received read_mem_cb: ADDR 'hf301900000000800, NDW 'h20, FBE 'hf, LBE 'hf 
AVY_INF: @86814.003ns : RC received read_mem_cb: ADDR 'hf301900000000880, NDW 'h20, FBE 'hf, LBE 'hf 
AVY_INF: @86826.003ns : RC received read_mem_cb: ADDR 'hf301900000000900, NDW 'h20, FBE 'hf, LBE 'hf 
AVY_INF: @86838.003ns : RC received read_mem_cb: ADDR 'hf301900000000980, NDW 'h20, FBE 'hf, LBE 'hf 
AVY_INF: @86850.003ns : RC received read_mem_cb: ADDR 'hf301900000000a00, NDW 'h20, FBE 'hf, LBE 'hf 
AVY_INF: @86866.003ns : RC received read_mem_cb: ADDR 'hf301900000000a80, NDW 'h20, FBE 'hf, LBE 'hf 
...
AVY_INF: @89278.003ns : Read Data from QDMA BAR at address 'h12e8 with data 'h00010002 Done

AVY_INF: @89586.003ns : Read Data from QDMA BAR at address 'h1248 with data 'h0000000e Done
AVY_INF: @89586.003ns : Total H2C Decsriptor Count 14 from QDMA Register

 

Would you help me checking which configuration is wrong?  Please tell me if you need more information for debuging.


By the way, I notice Xilinx example design always uses single descriptor and single queue on task TSK_QDMA_MM_TEST during the testing (usp_pci_exp_usrapp_tx.v). It seems never run the case "single-queue and multi-descriptors" and "multi-queue and multi-descriptors". Are there anything steps or configuration I missed ? 

Thanks.

1 Solution

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Visitor wraoglter
Visitor
130 Views
Registered: ‎05-16-2018

Re: Multi-Descriptor of QDMA

Jump to solution

Hi all,

I fixed this issue, it is caused by my wrong configuration.

Thanks.

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1 Reply
Highlighted
Visitor wraoglter
Visitor
131 Views
Registered: ‎05-16-2018

Re: Multi-Descriptor of QDMA

Jump to solution

Hi all,

I fixed this issue, it is caused by my wrong configuration.

Thanks.

0 Kudos