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Anonymous
Not applicable
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Multiple Interrupt Handling with PCIe

I amimplementing BMD design as explained in xapp1052(v2.5). Have implemented thedesign on AvnetV5LXT/SXT PCIe Development Board using the PCIe. Have generated the EndpointBlock plus for PCIe 1.9 using ISE 10.1. I have been successful in running the BMDdesign with both the legacy interrupts and Message signal interrupts usingsingle vector.

 

The application which I am working ongenerates multiple interrupts in the RTL to the host application. So far I haveassigned only one vector to the all the interrupts in the RTL design due towhich after receiving the interrupt at the application end I have to go andcheck a register to see which interrupt has occurred. I don’t want myapplication to go and read the register rather it should know which interrupthas occurred. Now as per the understanding developedthrough the document of PCIe endpoint, there are interrupts vectors that needto be generated at the time of PCIe core generation in order to assign eachinterrupt a different vector. The questions I need to ask are as follow:

 

·        How tolink the multiple interrupts in the RTL with the multiple vectors of the MSI?

 

·        Are thereany changes need to be made in the RTL design?

 

·        Is thereany reference material that could help me doing this ?

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Xilinx Employee
Xilinx Employee
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Registered: ‎09-02-2009

Hi Usama,

 

Check out the Block Plus Users Guide as it has some examples of how to use MSI.  Here are a couple of other gotchas to avoid as well.

 

When you select how many vectors you are requesting, that does not guarantee how many you will receive.  So in theory, you will need to scale back the number of interrupts you support to one.

 

Once you know how many interrupts you have been alotted to your design by the system (cfg_interrupt_mmenable[2:0] output) and if MSI is enabled (cfg_interrupt_msienable output) you can create MSI interrupts.

 

The vector you want to send should be driven on the following input to the block - cfg_interrupt_di[7:0].  Cfg_interrupt_n and cfg_interrupt_rdy_n are the control signals used to determine when the core has accepted the vector.  Once the PCIe block asserts cfg_interrupt_rdy_n indicating it has accepted the vector, it will generate a message to the Host with the vector supplied.

 

There is a much better explanation in the Users Guide, but hopefully this will get you started.

 

Jason

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Anonymous
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thanx jason i am not clear on 1 point that is the vector which i want to generate is system depended or core dependent?? can u clear me on this. and if it is system dependent than do u know any other method that i can use in order recieve interrupts up at the application level without going back to the hardware and reading it from there that which interrupt has occured.

 

 

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Xilinx Employee
Xilinx Employee
7,930 Views
Registered: ‎09-02-2009

Hi Usama,

 

The number of vectors requested is core dependent (via the Coregen GUI).  The number of vectors the core is allotted is system dependent(the system writes the value into the appropriate configuration register) .  The value you choose for the interrupt is dependent on your design (the value on cfg_interrupt_di[7:0]).

 

So in an open system, you will need to scale back the interrupts if the design is not fully allotted all of it's requested interrupts.  I suppose in a closed system, you will know if you will get all of the interrupts that were requested.  If this is the case, the software should be able to look at the origination address of the interrupt and the vector to determine what the interrupts means.

 

Hope this answers your question.

 

Jason

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Anonymous
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hi Jason ,

 

 

thanks for the help.

 

i have made the changes in the RTL code as per my understanding. what i have done is i have reserved a register from which i generate a pulse by writing from the user application. this pulse causes the interrupt to generate in parallel i have created a counter which is incremented every time i generate the pulse. the value of the counter is assigned to  cfg_interrupt_di[7:0]. When i run this on the FPGA i get the following waveform on the chipscope 

 

 

Now what I wanna know is

 

 

  • is it the right way? or i have to do some other changes in the RTL.
  • how can i check that how much vectors can my system generate cause i am getting only value 0 against the signal cfg_interrupt_mmenable[2:0] .
 
 

 

untitled.bmp
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Anonymous
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Another thing which i need to know is that i am using Jungo Windriver to generate the inf file for my application. Is it the limitation of the Jungo Windriver libraries that my system is not getting more than 1 interrupt vector
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Xilinx Employee
Xilinx Employee
7,833 Views
Registered: ‎09-02-2009

Hi Usama,

 

I don't have a lot of knowledge on the software side of things so I am not sure why MSI is not being enabled in your system.  It could be the software or it could be that the chipset does not support MSI.  Do you know the chipset that is being used in your system?

 

Jason

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