cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
dongzhiqing
Visitor
Visitor
9,771 Views
Registered: ‎05-11-2011

My computer can not start when using pcie board(pcie​_v5lx50t)​,help!!!

   If I do not download the core,It can start.But if I download the core pcie block pluse  v1.14  X8  using ise11.1(in pcie x16 slot),it can not start. I think BIOS test does not finish,because the leds on the keyboard does not flash.When using the Logic Analyzer,it indicates that the signals "trn_lnk_up_n" and"cfg_pcie_link_state[2:0]" are all in high level.

   If in x1 slot using  pcie block pluse  v1.14  X1,the computer can start,but it can not find the device.

  What's the problem?Thank you!    

0 Kudos
18 Replies
scollinson
Contributor
Contributor
9,765 Views
Registered: ‎11-08-2010

Are you sure you met all the timing constraints when implementing your design? If your computer is trying to read and write to the configuration space of your device and it is not responding (correctly or at all) this could cause your computer to freeze at boot.
0 Kudos
dongzhiqing
Visitor
Visitor
9,762 Views
Registered: ‎05-11-2011

In fact the impedance is 109 ohms,is that the problem? 

0 Kudos
luisb
Xilinx Employee
Xilinx Employee
9,750 Views
Registered: ‎04-06-2010

I don't want to rule out the impedence being a problem, however, I would not look there first.  

 

I would first take a known and working design and download it to your board.  I would first start off with the example design that comes with the core.  If you generate the core in CoreGen Standalone, you'll actually get a directory structure of files.  Go to the following diretory and run the implement.bat script.

<core name>/implement/

 

I would also double check the pinouts that come with example design and make sure that they match your board.

 

If this doesn't work, let us know more information about your chipset.

0 Kudos
colorfulnmr
Visitor
Visitor
9,739 Views
Registered: ‎05-13-2011

I have tried what you said,but it  still doesn't work. My chipset is INTEL  E5300. THANK YOU!

1.jpg
0 Kudos
colorfulnmr
Visitor
Visitor
9,738 Views
Registered: ‎05-13-2011

 This pitcure is the power sch.Thank you!

2.jpg
0 Kudos
luisb
Xilinx Employee
Xilinx Employee
9,724 Views
Registered: ‎04-06-2010

When you generated the example design, did you verify that the UCF was correct?

You need to make sure that the placement of the GTs and the PCIe hardblock are correct.

You should also make sure that the reset is constrained to the correct pin

 

Did you also ensure that you chose a 100Mhz refclk?  From your schematic, it looks like you're using the slot clock directly.

0 Kudos
colorfulnmr
Visitor
Visitor
9,718 Views
Registered: ‎05-13-2011

Hello there!I have checked many signals in the core. I find that when the refclkout ,system reset and trn_reset are normal,the trn_clk signal is always in low level,not the default frequence 62.5MHz.Why did this happen?

0 Kudos
colorfulnmr
Visitor
Visitor
9,715 Views
Registered: ‎05-13-2011

The clock_lock and pll_lock keep in low level.

0 Kudos
luisb
Xilinx Employee
Xilinx Employee
9,711 Views
Registered: ‎04-06-2010

If the clocks are not locking, then it's possible that the location constraint of the REFCLK is incorrect.   The other option is that the REFCLK is at the wrong frequency.  It's also possible that the refclk has too much jitter to lock the PLLs in the GT.

0 Kudos
dongzhiqing
Visitor
Visitor
8,505 Views
Registered: ‎05-11-2011

Thank you for your reply! From the schematic,I am using the clock from the slot connecting the GTP-X0Y3.The clock signal refclkout from PCIE *1is really  worse than in PCIE*8.Cause the PCIE*1 is using the GTP-X0Y2. But the datasheet says  2 neighboring GTPS gap is ok.Why is it so worse than PCIE*8? 

0 Kudos
luisb
Xilinx Employee
Xilinx Employee
8,495 Views
Registered: ‎04-06-2010

If you're forwarding a reference clock from an unused GTP, I would recommend reading through the following AR:

http://www.xilinx.com/support/answers/33473.htm

 

Hope this helps.

0 Kudos
colorfulnmr
Visitor
Visitor
8,489 Views
Registered: ‎05-13-2011

Thank you very much.I have finished the task and the refclkout is better.But the trn_clk is still in low level and always does not change.I am so frustrated!!!

0 Kudos
luisb
Xilinx Employee
Xilinx Employee
8,485 Views
Registered: ‎04-06-2010

trn_clk comes from the PLL.  I would check with ChipScope if this PLL is held in reset for some reason.  Check the plllkdet signal from the GTP as well.

0 Kudos
dongzhiqing
Visitor
Visitor
8,473 Views
Registered: ‎05-11-2011

 I have confidence now. The signal GTPRESET is normal, but the signal  pll_lock is always in low level.Which signal should I check?

0 Kudos
luisb
Xilinx Employee
Xilinx Employee
8,465 Views
Registered: ‎04-06-2010

You said that refclkout is better, but plllkdet is not asserted.  plllkdet is asserted when the refclkout of the GT is stable and clean. 

 

I would like to have a look at your XCO and your UCF.  Can you attach these?

0 Kudos
colorfulnmr
Visitor
Visitor
8,462 Views
Registered: ‎05-13-2011

 
0 Kudos
colorfulnmr
Visitor
Visitor
8,461 Views
Registered: ‎05-13-2011

Every morning the first thing I do is checking this topic.Thank you!
Here is my ucf.I am using ISE13.1 WebPack.
I also want to try  using an externa 100Ml OSC to connect to GTP CLKIN.

0 Kudos
luisb
Xilinx Employee
Xilinx Employee
8,457 Views
Registered: ‎04-06-2010

I looked over your design and I couldn't find anything wrong with it.  Here's what I suggest double checking:

 

1. Make sure your reset pin is on pin N4

2. Make sure your power rails are at the voltage you're expecting and not dropping.  You're only using 1 transceiver, so it should be pretty solid.

3. Make sure there's a refclk coming in.

 

If this doesn't lead you to anywhere I would open a case with Xilinx Technical Support and ask why plllkdet is not asserting.  If this is not asserting, then there's something fundamentally wrong on the hardware side of things.  Either an incorrect schematic, power, signal integrity, or grounding problem.  

 

I would not suggest using an exernal clock.  I highly recommend keeping the system synchronous and using the clock that's provided.

0 Kudos