05-11-2011 10:35 PM
If in x1 slot using pcie block pluse v1.14 X1,the computer can start,but it can not find the device.
What's the problem?Thank you!
05-12-2011 04:16 PM
05-17-2011 07:19 AM
I don't want to rule out the impedence being a problem, however, I would not look there first.
I would first take a known and working design and download it to your board. I would first start off with the example design that comes with the core. If you generate the core in CoreGen Standalone, you'll actually get a directory structure of files. Go to the following diretory and run the implement.bat script.
I would also double check the pinouts that come with example design and make sure that they match your board.
If this doesn't work, let us know more information about your chipset.
05-23-2011 09:09 AM
When you generated the example design, did you verify that the UCF was correct?
You need to make sure that the placement of the GTs and the PCIe hardblock are correct.
You should also make sure that the reset is constrained to the correct pin
Did you also ensure that you chose a 100Mhz refclk? From your schematic, it looks like you're using the slot clock directly.
05-23-2011 11:16 PM
Hello there!I have checked many signals in the core. I find that when the refclkout ,system reset and trn_reset are normal,the trn_clk signal is always in low level,not the default frequence 62.5MHz.Why did this happen?
05-24-2011 11:11 AM
If the clocks are not locking, then it's possible that the location constraint of the REFCLK is incorrect. The other option is that the REFCLK is at the wrong frequency. It's also possible that the refclk has too much jitter to lock the PLLs in the GT.
05-24-2011 06:50 PM
Thank you for your reply! From the schematic,I am using the clock from the slot connecting the GTP-X0Y3.The clock signal refclkout from PCIE *1is really worse than in PCIE*8.Cause the PCIE*1 is using the GTP-X0Y2. But the datasheet says 2 neighboring GTPS gap is ok.Why is it so worse than PCIE*8?
05-25-2011 09:05 AM
05-26-2011 03:13 AM
Thank you very much.I have finished the task and the refclkout is better.But the trn_clk is still in low level and always does not change.I am so frustrated!!!
05-26-2011 08:46 AM
trn_clk comes from the PLL. I would check with ChipScope if this PLL is held in reset for some reason. Check the plllkdet signal from the GTP as well.
05-27-2011 03:30 PM
You said that refclkout is better, but plllkdet is not asserted. plllkdet is asserted when the refclkout of the GT is stable and clean.
I would like to have a look at your XCO and your UCF. Can you attach these?
05-27-2011 06:08 PM
05-28-2011 05:43 AM
I looked over your design and I couldn't find anything wrong with it. Here's what I suggest double checking:
1. Make sure your reset pin is on pin N4
2. Make sure your power rails are at the voltage you're expecting and not dropping. You're only using 1 transceiver, so it should be pretty solid.
3. Make sure there's a refclk coming in.
If this doesn't lead you to anywhere I would open a case with Xilinx Technical Support and ask why plllkdet is not asserting. If this is not asserting, then there's something fundamentally wrong on the hardware side of things. Either an incorrect schematic, power, signal integrity, or grounding problem.
I would not suggest using an exernal clock. I highly recommend keeping the system synchronous and using the clock that's provided.