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swamy
Visitor
Visitor
274 Views
Registered: ‎07-02-2021

Need design to get same functionality of AXI MM PCI IP using 7 series Integrated PCI IP

Hi,

I am working on Artix7 with the AC701 development board.

My design requires PCIe IP with AXI Interface, for that, I am using AXI MM PCIe IP and now I want to reduce LUT utilization.
From Artix7 spec, there is an integrated PCIe IP available as hard IP. Shall I use this to reduce LUT utilization?
Which AXI IP suitable to achieve the same AXI MM PCIe IP to interface with 7 series Integrated PCIe IP?

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2 Replies
nmanitri
Xilinx Employee
Xilinx Employee
233 Views
Registered: ‎06-13-2018

Hi @swamy ,

We have PCIe AXI MM IP. Could you please create an example design and check how much resource it is using, then compare it with your design. 

In the meanwhile, could you please share your utilization report and your xci file.

Regards,

Naveen 

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necare81
Voyager
Voyager
226 Views
Registered: ‎03-31-2016

The AXI MM PCIe IP is a wrapper that already includes the Integrated PCIe IP.

You can adjust some of the option in the AXI MM bridge IP to try to reduce resource utilization,  narrower links with smaller buffers or outstanding transactions should help.

There are some older example designs that bridge the Integrated PCIe IP to AXI-MM you might be able to be modified to give lower resource usage than the more recent IP but you will not find a IP that gives lower resource usage by using the integrated PCIe because all the IPs already use that.  I don't think Xilinx has a fully soft PCIe IP for any of the more recent FPGA families.

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