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RTdesignengr
Observer
Observer
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Registered: ‎11-13-2018

No descriptor fetch requests seen

I am running a simulation for a design with the DMA/Bridge Subsystem for PCIe v4.1 in it. I am using vivado 2019.2. The XDMA is configured to run in memory mapped mode and 4 lanes. On the other end I have a PCIe QVIP from mentor. I am able to get user link up go high and I am able to talk to the xdma over BAR 1 because I can make bit 6 of c2h_sts output (control register 'Run" bit) go high by setting the 'Run" bit in the C2H channel control register (bit 0). The issue that I facing is that after the run bit is set, I do not see any descriptor fetch requests coming from the XDMA. I do have the scatter-gather list setup. 

I read the C2H channel status register and I see only bit 0; which is the SGDMA busy bit; set and the rest are all zero. Please advise

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andrewjyoung2
Visitor
Visitor
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Registered: ‎04-17-2019

Hahaha, is that you Ravi?

If so, yep the card to host status port reads 0x41 and the BAR1 status register reads 0x1. So the DMA engine is enabled and both the status port of the XDMA block and the BAR1 status register know that it's on.

 

mmcnicho
Xilinx Employee
Xilinx Employee
227 Views
Registered: ‎10-09-2019

This issue is being worked as an SR.

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