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scriptblue
Visitor
Visitor
9,692 Views
Registered: ‎02-12-2010

Not being detected (Spartan 6 LXT, SP605)

I purchased an SP605 a while ago, and haven't been able to get the PCIe block to work. I've tested the board in two machines, an embedded motherboard with an Intel Atom and a desktop Core 2 Duo, and neither of them seems to be able to see the SP605 board. I've followed xtp065 to a tee. I've also implemented the core through the example project created by the core generator, that didn't seem to work either. Either way the I've failed to see the core enumerate on either platform. The embedded Intel Atom computer will boot in two to three times its normal time, additionally other PCIe network adapters seem to disappear from lspci. The Core 2 Duo desktop however does not seem to even acknoledge the card's existence.

 

Also according to the LEDs, trn_lnk_up_n is '1'.

 

Any ideas as to what could be going wrong?

Edit: it seems to be working in my Core 2 Duo machine. However the embedded machine still seems to be acting weird, ie. disconnecting my network adapters when I (hot/cold) plug the FPGA.

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19 Replies
Anonymous
Not applicable
9,670 Views

Have you tried by downloading the pcie design bit file provided in the link below?

 

http://www.xilinx.com/products/boards/sp605/reference_designs.htm

 

 

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scriptblue
Visitor
Visitor
9,423 Views
Registered: ‎02-12-2010

Yes I have, I also bought a brand new computer just for development purposes. It seems that any computer built after 2006 will not work with the SP605. Have you guys considered doing some testing before releasing this product?

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luisb
Xilinx Employee
Xilinx Employee
9,415 Views
Registered: ‎04-06-2010

It's hard to say what the problem is without getting chipscope in your design, but I would try disabling ASPM and also disabling Spread Spectrum clocking.  Have you tried this out yet?

 

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scriptblue
Visitor
Visitor
9,399 Views
Registered: ‎02-12-2010

I have disabled Spread Spectrum clocking, and it seems that ASPM is not active either (at least according to a grep of lspci -vvv). Which signals would you suggest I look at while chipscoping?

 

Just to clarify, the device is not showing up under lspci, I am looking at the Root complex's capabilities.

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luisb
Xilinx Employee
Xilinx Employee
9,390 Views
Registered: ‎04-06-2010

I would grab the signals going to the PIPE interface to the GTP.

I would search within chipscope analyzer with the following signals:

 

plllkdet

ltssm

pipe*tx*data or just tx*data

pipe*tx*k or just     tx*char*is*k

pipe*rx*data or just rx*data

pipe*rx*k or just     rx*char*is*k

txelecidle

rxelecidle

rxstatus

 

First make sure that plllkdet is asserting. This is the PLL within the GTP.

Then make sure rxstatus is always all zeros.

Then look at ltssm and see what states it's getting stuck at.

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scriptblue
Visitor
Visitor
9,369 Views
Registered: ‎02-12-2010

I am unable to get any readings through Chipscope because the ILA which is clocked against trn_clk does not seem to be working, and I can't clock against the output of SYS_CLK because the output of the IBUFDS can only go to the GTP.

 

I've used both 1.4 (TLP) and 2.2 (AXI) versions of this core but they both require that I set the following option in the UCF.

PIN "s6_pcie_v2_2_i/phy_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;

Could this be causing problems? I'm only trying to clock against trn_clk / user_clk.

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deepeshm
Xilinx Employee
Xilinx Employee
9,333 Views
Registered: ‎08-06-2008

Could you let us know how you are programming the device? JTAG, PROM, Compact Flash?

 

Thanks

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scriptblue
Visitor
Visitor
9,316 Views
Registered: ‎02-12-2010

I usually just turn the PC on, then directly JTAG the board, and reboot the computer. This is the only way I've gotten it to work in my older machine.

 

From the looks of it, it seems as if none of the CLKs are working. I've tried using trn_clk, clk_62_5, as well as the GTP's clock. Could you please suggest a clock source?

 

PS. trn_lnk_up_n (led_2 in the design) is the only lit LED.

 

Lastly, how could a clock that doesn't lock knock out an entire segment of the PCIe bus?

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luisb
Xilinx Employee
Xilinx Employee
9,290 Views
Registered: ‎04-06-2010

I would double check three things.

1. Your schematic and check where your Refclk is coming in.

2. Your UCF to see where the Refclk is contrained to.

3. The frequency of Refclk matches what you selected when you generated the core.

Hope this helps.
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scriptblue
Visitor
Visitor
9,408 Views
Registered: ‎02-12-2010

My schematic is your schematic, I have not modified the Xilinx SP605 board. Shouldn't the vhdl example that comes with the 1.4 version of the core have the correct UCF?
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luisb
Xilinx Employee
Xilinx Employee
9,393 Views
Registered: ‎04-06-2010

I believe there's an option when you generate the core to select the SP605. Did you make this selection in the Coregen GUI?
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deepeshm
Xilinx Employee
Xilinx Employee
9,386 Views
Registered: ‎08-06-2008

As Luis suggested please check UCF and also enable SP605 when you generate the core. I tried downloading reference design bit file in one of my SP605 boards, it worked all fine. I would also suggest to check the board configuration as mentioned in the links below:

 

http://www.xilinx.com/support/documentation/boards_and_kits/xtp089.pdf

http://www.xilinx.com/support/documentation/boards_and_kits/ug525.pdf

 

Thanks.

 

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scriptblue
Visitor
Visitor
9,369 Views
Registered: ‎02-12-2010

Assuming the UCF that comes prepackaged with the core and its example is way off. Why won't the the targetted reference designs work? I used the CES version because my board uses a CES S6. (http://www.xilinx.com/products/boards/s6conn/reference_designs.htm). Other than that I have tested the board using the diagnostic tool and it seems to work fine, and I've had people double check my UCF. I unfortunately do not own an oscilloscope powerful enough to scope the crystal.

Is there anything that could be done now that Webcase has stopped answering my messages?

 

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deepeshm
Xilinx Employee
Xilinx Employee
9,355 Views
Registered: ‎08-06-2008

The reference design should work out of the box. As I mentioned in my previous post, it works for me and we have many customers getting it to work correctly. Unfortunately there seems to be some problem at your side. I assume you have checked all the board setup according to the links I posted in the previous post. If you haven't done so, please check it again. Provided the system is fine and there is no signal integrity issue on the board, the only problem could be the incorrect board setup. If it still doesn't work, I would suggest to grab ltssm and trn_lnk_up_n signal in chipscope. 

 

Once you generate the default core in Coregen for SP605 board, please follow the steps mentioned below to capture the above signals:

 

http://www.xilinx.com/support/answers/35212.htm

 

Could you also confirm you are seeing this problem in multiple machines or only one machine?

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scriptblue
Visitor
Visitor
9,343 Views
Registered: ‎02-12-2010

I am unable to chipscope the device because none of the clocks work. I have been able to reproduce this problem without fail on 4 different machines.

 

Edit: Could you please confirm whether or not these boards were tested before being sold?

When I say I'm unable to chipscope, I mean to say Chipscope (once inserted, synthesized, flashed, and executed) will not arm because there is no clock signal on trn_clk.

 

Why is webcase no longer responding to my emails?

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scriptblue
Visitor
Visitor
9,312 Views
Registered: ‎02-12-2010

I'm trying to write a simple counter working so I can check REFCLK programatically, but when I try the following code

 

    process(sys_clk_c)
    begin
        if (rising_edge(sys_clk_c)) then
            pre_count <= pre_count + "1";
        end if;
    end process;

  refclk_ibuf : IBUFGDS
  port map
  (
    O  => sys_clk_c,
    I  => sys_clk_p,
    IB => sys_clk_n
  );

 


 

 

I get the following errors

 


ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOB component because the site type selected is not compatible.

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   IOB was chosen because the IO contains symbols and/or properties consistent
   with input, output, or bi-directional usage and contains no other symbols or
   properties that require a more specific IO component type. Please double
   check that the types of logic elements and all of their relevant properties
   and configuration options are compatible with the physical site type of the
   constraint.

   Summary:
   Symbols involved:
       PAD symbol "sys_clk_n" (Pad Signal = sys_clk_n)
       SlaveBuffer symbol "refclk_ibuf/SLAVEBUF.DIFFIN" (Output Signal =
   refclk_ibuf/SLAVEBUF.DIFFIN)
(Output
   Signal = your_instance_name/clkin1_buf0/SLAVEBUF.DIFFIN)
   Component type involved: IOB
   Site Location involved: B10
   Site Type involved: IPAD

 


 

 

 

I get another error that looks just like this for sys_clk_p. Is there anyway to use the differential system clk to drive a counter?

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deepeshm
Xilinx Employee
Xilinx Employee
9,300 Views
Registered: ‎08-06-2008

Could you please check if plllkdet_out signal is asserted or not? If this signal is asserted, it will tell us your input reference clcok is present and running correctly. I have attached here a screen shot from chipscope inserter that shows the signal.

pll_det.PNG
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ywu
Xilinx Employee
Xilinx Employee
9,294 Views
Registered: ‎11-28-2007

Pin A10 and B10 are MGT reference clock inputs. You can't use them to directly drive FPGA fabric. The SP605 board has a 200MHz diff clock source (see UCF constraint below) that you can use for internal logic.

 

NET "SYSCLK_N" LOC = "K22"; ##
NET "SYSCLK_P" LOC = "K21"; ##

 

 

You can find more details from the SP605 user guide below:

 

http://www.xilinx.com/support/documentation/boards_and_kits/ug526.pdf

 

 

 

 


@scriptblue wrote:

I'm trying to write a simple counter working so I can check REFCLK programatically, but when I try the following code

 

    process(sys_clk_c)
    begin
        if (rising_edge(sys_clk_c)) then
            pre_count <= pre_count + "1";
        end if;
    end process;

  refclk_ibuf : IBUFGDS
  port map
  (
    O  => sys_clk_c,
    I  => sys_clk_p,
    IB => sys_clk_n
  );

 


 

 

I get the following errors

 


ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOB component because the site type selected is not compatible.

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   IOB was chosen because the IO contains symbols and/or properties consistent
   with input, output, or bi-directional usage and contains no other symbols or
   properties that require a more specific IO component type. Please double
   check that the types of logic elements and all of their relevant properties
   and configuration options are compatible with the physical site type of the
   constraint.

   Summary:
   Symbols involved:
       PAD symbol "sys_clk_n" (Pad Signal = sys_clk_n)
       SlaveBuffer symbol "refclk_ibuf/SLAVEBUF.DIFFIN" (Output Signal =
   refclk_ibuf/SLAVEBUF.DIFFIN)
(Output
   Signal = your_instance_name/clkin1_buf0/SLAVEBUF.DIFFIN)
   Component type involved: IOB
   Site Location involved: B10
   Site Type involved: IPAD

 


 

 

 

I get another error that looks just like this for sys_clk_p. Is there anyway to use the differential system clk to drive a counter?


 

Cheers,
Jim
scriptblue
Visitor
Visitor
9,286 Views
Registered: ‎02-12-2010

dmsxilinx, what should I use for a clock signal?

 

Edit: I used the 200MHz clock, this is the chipscope output I get.

 

IBERT indicates that the near end PCS and PMA loopback modes both work with no bit errors.

 

I have been able to measure an output voltage across PCIE_TX_P and PCIE_TX_N when placing GTPA1_DUAL_X0Y0_0 into Far-End PMA mode.

xilinx.png
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