11-02-2020 09:48 PM
I need to design a Zinq Ultrascale (master) board that will drive four PCIe endpoint devices (slave).
Can I use a chip with four PCIe blocks for this (for ex. XCZU17EG) ?
What type of each of four PCIe block must be in this example (master_endpoint <-> slave_endpoint or master_root_complex <-> slave_endpoint)?
Thanks for answer!
11-03-2020 06:36 PM
It is possible to implement four independent endpoints. However, the layout is limited depending on the lane width, so please use Example design to check the placement of the reference clock, etc. It may need to supply multiple reference clocks.
11-04-2020 12:47 AM
ok, i've verified xczu17eg-ffvd1760, that's support 4 X4 PCIe independent blocks, so you tell that i can design four independent PCIe master-slave endpoints connections to other FPGA with PCIe endpoint?