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ajellisuk
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Registered: ‎06-01-2018

Opening a PCIe-EP project in Xilinx ISE 14.7

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Hello

 

I have generated a PCIe EP project using the Xilinx Core generator by following the steps in "sp605_PCIe_Gen1_x1_pdf_xtp065_13.4_c.pdf"

 

Whilst I'm able to build the project using implement.sh and load into the flash, I'm not able to open the project in Xilinx ISE 14.7. If I click "Open Project" in ISE and browse to the PCIe EP folder I've created I see 2 files:

1) s6_pcie_v2_4_vhdl_example_project.xise
2) s6_pcie_v2_4.xise

 

If I try and open the first file I get the following message:

isecapture.png

 

If I click either Migrate Only, or Backup and Migrate I get the following message in ISEs console:

"Beginning migration of s6_pcie_v2_4_vhdl_example_project.xise
ERROR: migrating /home/ise/sf_EG7590/VHDL/PCIe_EP/s6_pcie_v2_4_vhdl_example_project.xise failed, could not generate original project information."

I have spent some time trying to resolve this issue without success.

 

Can someone please enlighten me as to how I can open the PCIe EP project in ISE 14.7

 

I'm using windows 10, so I'm running ISE 14.7 in the ISE virtual machine running redhat Linux and a directory share from the host Win10 system to Virtual box

 

Thanks in advance

 

Andrew

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venkata
Moderator
Moderator
753 Views
Registered: ‎02-16-2010
Could you try to generate the design in ISE14.7 based on the steps mentioned in sp605_PCIe_Gen1_x1_pdf_xtp065_13.4_c.pdf?
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venkata
Moderator
Moderator
754 Views
Registered: ‎02-16-2010
Could you try to generate the design in ISE14.7 based on the steps mentioned in sp605_PCIe_Gen1_x1_pdf_xtp065_13.4_c.pdf?
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ajellisuk
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Registered: ‎06-01-2018

Hello,

 

I believe I may have been going around things the wrong way. Rather than trying to open the generated project in ISE, I believe that I should instead add the generated cor to another project which I've managed to do.

 

I'm not sure how to interface my own code to the pcie core, but that question is for a separate thread.

 

Thanks

 

Andrew

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