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chamber_yang
Visitor
Visitor
299 Views
Registered: ‎03-21-2021

Our IP can not access Host through S_AXI_BRIDGE

Hi Sir

I use vivado 2020.02 to build a block design at VM1802 platform, and simulate with it.

Using VERSAL ACAP XDMA Subsystem for PCIe and enable Bridge slave mode.

But Our IP can not access host memory through S_AXI_BRIDGE because AXI bus always response read error.

How to fix it?

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3 Replies
mmcnicho
Xilinx Employee
Xilinx Employee
239 Views
Registered: ‎10-09-2019

Hi,

Are you using the IP example design?

Also, can you attach a screenshot of the failing transaction.

Thanks!

chamber_yang
Visitor
Visitor
197 Views
Registered: ‎03-21-2021

Hi Sir

I found VM1802's XDMA PCIe IP connect with smart connect IP, its C_AXIBAR_HIGHADDR_0 need to modify otherwise the address can not over 0x1000.

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mmcnicho
Xilinx Employee
Xilinx Employee
61 Views
Registered: ‎10-09-2019

Hi,

I want to check if I understand correctly. Were you able to resolve your issue by modifying  C_AXIBAR_HIGHADDR_0?

Thanks!

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