03-29-2021 11:10 PM
I use vivado 2020.02 to build a block design at VM1802 platform, and simulate with it.
Using VERSAL ACAP XDMA Subsystem for PCIe and enable Bridge slave mode.
But Our IP can not access host memory through S_AXI_BRIDGE because AXI bus always response read error.
How to fix it?
04-05-2021 06:13 PM
I found VM1802's XDMA PCIe IP connect with smart connect IP, its C_AXIBAR_HIGHADDR_0 need to modify otherwise the address can not over 0x1000.