10-23-2017 04:55 AM
Hi to all
I've connected a Xilinx ZC706 with a PowerPC 64bit board using the PCIe bus.
The ZC706 is the endpoint and the PowerPC is the host.
I'm using Linux as operating system and the XDMA (AR# 65444) as a device driver.
Unfortunately each time I try to exchage data, the PCI return an error code: the inboud transaction seems not correctly mapped.
I've not met problems reading and writing the pci registers without the DMA.
The same driver with the same board works well if I use a standard x86_64 PC as a host.
Analyzing the log messages i didn't find anything strange.
Can someone help me? Any kind of suggestions will be apprectiated.
Logs are attached.
01-22-2018 02:10 AM
I was facing a similar problem on ppc e500v2 and your log files comparing x86 were helpful in diagnosing and fixing my problem. Although your architecture is not identical I will post my solution here as this was the top post with all the right keywords so it may help those facing similar issues.
I believe there is a bug in the driver which causes an endian conversion to happen twice on big-endian architectures when setting the address of the first descriptor.
w = cpu_to_le32(PCI_DMA_L(transfer->desc_bus)); write_register(w, &engine->sgdma_regs->first_desc_lo);
The registers must be written in LE format but write_register already does this correctly (by calling iowrite32) so the additional cpu_to_le32 causes a byte-swap to happen twice. This was resulting in the engine using the incorrect address for the first descriptor. The engine status dump will then show MAGIC_STOPPED (as it failed to find a valid descriptor at the given address). This would not be an issue on LE platforms (e.g. x86) where the format is already natively correct and in both cases no actual conversion is performed.
16: transfer_create():transfer->desc_bus = 0x100ea66a000 ... 54: engine_reg_dump(): H2C0: ioread32(0x8000080088c40004) returned 0x00f83e1e (control) 55: engine_reg_dump(): H2C0: ioread32(0x8000080088c44080) returned 0x00a066ea (first_desc_lo) 56: engine_reg_dump(): H2C0: ioread32(0x8000080088c44084) returned 0x00010000 (first_desc_hi)
We can see the control register looks correct but the endianness of the descriptor address register has been byte-swapped.
In my case the attached patch fixed this and enabled the run_tests script to pass all loopback tests.