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Newbie
Newbie
6,358 Views
Registered: ‎05-14-2009

PCI Express DMA Completion streaming problem

Hi,

I am implementing PCIe DMA engine with the following parameters:
 - Virtex5 PCI Express Endpoint Block
 - x8 lane width
 - 250Mhz interface frequency
 - EndpointBlock Plus for PCI Express v1.9

The endpoint initializes with x8 lane width, PIO/DMA transfers are passing through.
Following the xapp859 I am  trying to reach it's upstream performance and I am configuring the PCIe IP with either "None" or "One Posted/Non-Posted Header Credit" advanced flow control setting. Also the trn_rnp_ok_n and trn_rcpl_streaming_n signals are tied to 0 (as in the xapp859 implementation and as advised in the UG341). And the trn_rdst_rdy_n signal is never deasserted as all inbound packets are drained immedeately from the transaction interface. The DMA engine sends a read request with Relaxed Order bit set to 1, for example:

    00 00 20 80 - (Fmt/Type = 7'b00_00000 - 3DW/MRd, TC = 3'b000,TD = 1'b0, EP = 1'b0, Attr = 2'b10 - Relaxed Order/Default No snoop attribute, Length = 10'b0010000000 - 128 bytes)
    04 00 00 FF - (Requester ID = 16'h0400, Tag = 8'h00, Last DW BE = 4'b1111, First DW BE = 4'b1111)
    09 5F 90 00 - (Address)

The completion packets received are not malformed and contain the right payload. But no Completion Streaming seems to occur as there is considerable delay between the CplD packets and no packet burst occurs, as there are no back-to-back transfers observed like the ones shown on the diagrams in the xapp859 documentation.

Is there something else that has to be set up or am I missing something?

 

Thanks!

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3 Replies
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Observer
Observer
5,314 Views
Registered: ‎06-07-2010

Hi alekskazan

 

I am implementing a similar system with DMA reads initiated by a downstream endpoint reading from PCs main memory using the xc5v95sxt pcie endpoint. I'm experiencing a read completion round trip delay of 2.5 – 3.0 us. I can’t see where this delay is introduced.

 

alekskazan, did you get any solution on your completion problem you reported back in May 2009?

 

Best Regards,

estrup

 

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Xilinx Employee
Xilinx Employee
5,298 Views
Registered: ‎02-01-2010

Not that I expect this to fix your issue but you should upgrade your core to the most recent version of the tools if possible.

Out of curiosity is this in HW or Sim?

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Observer
Observer
5,295 Views
Registered: ‎06-07-2010

Hi,

 

I am using the very newest of everything....

 

This is HW...

 

Best Regards

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