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Visitor
Visitor
4,922 Views
Registered: ‎06-18-2009

PCI Express, DMA transfer, Downstream Port Model Simulation

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Hi,
I'm using the Downstream Port Model provided with the EndPoint Block plus V1.9 with patch V1.9 Rev 4.

 

I have severals problems to send memory a read request from the EndPoint to the Downstream Port. In the EndPoint point of view, I think to have properly sent all signals ( trn_td, trn_trem_n,  trn_tsof_n, trn_teof_n,  trn_tsrc_rdy_n, trn_tsrc_dsc_n) and check the signals (trn_tbuf_av(0), trn_tdst_rdy_n, trn_tdst_dsc_n). Moreover there are not error detected (cfg_dcommand). The maximum requested  number of data for each memory read request is 64Byte.

Even so, those requests don't appear in the Downstream Port trn_rd port. Moreover the signals trn_sof_n, trn_rsrc_rdy_n, trn_rd become 'X' after the first requests.


Thank you
Andrea
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Xilinx Employee
Xilinx Employee
5,655 Views
Registered: ‎08-01-2007

Hi Andrea,

 

You may want to be sure all of the inputs on the DSPort side of things are being driven to a known value (i.e. not left floating).  I've seen the trn_r* signals go to "X" in the past when inputs like trn_rnp_ok_n are not driven as a Non-posted packet comes in, for example.

 

-Kyle

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Xilinx Employee
Xilinx Employee
5,656 Views
Registered: ‎08-01-2007

Hi Andrea,

 

You may want to be sure all of the inputs on the DSPort side of things are being driven to a known value (i.e. not left floating).  I've seen the trn_r* signals go to "X" in the past when inputs like trn_rnp_ok_n are not driven as a Non-posted packet comes in, for example.

 

-Kyle

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Visitor
Visitor
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Registered: ‎06-18-2009

Hi Kyle,

 

thank you very much, now it works !!!

I left trn_rnp_ok_n input signal to DSPort floating.

 

Andrea

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